Re: [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth

On Mon, Mar 25, 2019 at 7:44 PM Wu Hao [off-list ref] wrote:

On Mon, Mar 25, 2019 at 12:50:40PM -0500, Alan Tull wrote:

quoted

On Sun, Mar 24, 2019 at 10:23 PM Wu Hao [off-list ref] wrote:

Hi Hao,

Looks good, one question below.

quoted

Current driver checks if input bitstream file size is aligned or
not per PR data width (default 32bits). It requires one additional
step for end user when they generate the bitstream file, padding
extra zeros to bitstream file to align its size per PR data width,
but they don't have to as hardware will drop extra padding bytes
automatically.

In order to simplify the user steps, this patch aligns PR buffer
size per PR data width in driver, to allow user to pass unaligned
size bitstream files to driver.

Signed-off-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Wu Hao <redacted>

Acked-by: Alan Tull <atull@kernel.org>

Thanks,
Alan