Thread (61 messages) 61 messages, 7 authors, 2021-03-17

Re: [dpdk-dev] [PATCH v6 2/2] bus/pci: support MMIO in PCI ioport accessors

From: Ferruh Yigit <hidden>
Date: 2021-02-19 08:52:52

On 2/9/2021 2:51 PM, Ferruh Yigit wrote:
On 1/29/2021 3:18 AM, 谢华伟(此时此刻) wrote:
quoted
From: "huawei.xhw" <redacted>

With IO BAR, we get PIO(programmed IO) address.
With MMIO BAR, we get mapped virtual address.
We distinguish PIO(Programmed IO) and MMIO(memory mapped IO) by their address 
like how kernel does.
ioread/write8/16/32 is provided to access PIO/MMIO.
By the way, for virtio on arch other than x86, BAR flag indicates PIO but is 
mapped.

Signed-off-by: huawei xie <redacted>
Reviewed-by: Maxime Coquelin <redacted>
<...>
quoted
+static inline void iowrite8(uint8_t val, void *addr)
+{
+    (uint64_t)(uintptr_t)addr >= PIO_MAX ?
+        *(volatile uint8_t *)addr = val :
+        outb(val, (unsigned long)addr);
Is the 'outb_p' to 'outb' conversion intentional? And if so why?

Same of the all 'outb_p', 'outw_p', 'outl_p'.
Reminder of above question.

Let's try to close this patch before release pressure hit again.
And as far as I understand already a new version is required for build errors on 
non x86 architectures.
<...>
quoted
              size = 1;
-#if defined(RTE_ARCH_X86)
-            outb_p(*s, reg);
-#else
-            *(volatile uint8_t *)reg = *s;
-#endif
+            iowrite8(*s, (void *)reg);
          }
      }
  }
  
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