-----Original Message-----
From: Phil Yang <redacted>
Sent: Monday, July 22, 2019 6:36 PM
To: dev@dpdk.org
Cc: thomas@monjalon.net; Jerin Jacob Kollanukkaran <redacted>;
gage.eads@intel.com; hemant.agrawal@nxp.com;
Honnappa.Nagarahalli@arm.com; gavin.hu@arm.com; nd@arm.com
Subject: [EXT] [PATCH v5 1/3] eal/arm64: add 128-bit atomic compare
exchange
----------------------------------------------------------------------
Add 128-bit atomic compare exchange on aarch64.

Suggested-by: Jerin Jacob <redacted>
Signed-off-by: Phil Yang <redacted>
Tested-by: Honnappa Nagarahalli <redacted>
Reviewed-by: Honnappa Nagarahalli <redacted>

diff --git a/config/common_base b/config/common_base index

8ef75c2..16dea5a 100644

--- a/config/common_base
+++ b/config/common_base

@@ -1067,3 +1067,8 @@ CONFIG_RTE_APP_CRYPTO_PERF=y  # Compile the

eventdev application  #  CONFIG_RTE_APP_EVENTDEV=y
+
+#
+# Compile ARM LSE ATOMIC instructions
+#
+CONFIG_RTE_ARM_FEATURE_ATOMICS=n

diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc

b/config/defconfig_arm64-octeontx2-linuxapp-gcc
index f20da24..a6508e8 100644

--- a/config/defconfig_arm64-octeontx2-linuxapp-gcc
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc

@@ -19,3 +19,6 @@ CONFIG_RTE_EAL_IGB_UIO=n

 # Max supported NIX LFs
 CONFIG_RTE_MAX_VFIO_GROUPS=128
+
+# arm64 LSE ATOMIC support
+CONFIG_RTE_ARM_FEATURE_ATOMICS=y

diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc

b/config/defconfig_arm64-thunderx2-linuxapp-gcc
index cc5c64b..17b6dec 100644

--- a/config/defconfig_arm64-thunderx2-linuxapp-gcc
+++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc

@@ -6,6 +6,7 @@

 CONFIG_RTE_MACHINE="thunderx2"

+CONFIG_RTE_ARM_FEATURE_ATOMICS=y
 CONFIG_RTE_CACHE_LINE_SIZE=64
 CONFIG_RTE_MAX_NUMA_NODES=2
 CONFIG_RTE_MAX_LCORE=256