Re: [PATCH v2 0/2] mlx5 high latency observed on send operations

On 8/27/2017 7:47 AM, Shahaf Shuler wrote:

from sagi@grimberg.me:

When measuring latency when running a latency critical workload on mlx5 pmd drivers we noticed high latency can occur due to delayed doorbell record update flush.

This can be reproduced using the simple program [1] against testpmd macswap fwd mode. This utility sends a raw ethernet frame to the dpdk port and measures the time between send and the received mirrored frame.

This patchset guarantees immediate doorbell updates visibility by making the doorbell a non-cacheble memory.
In addition, we relax the memory barrier for dma-able memory.

Without this fix the tsc delta was 3550760-5993019 cycles (which translates to 2-6 ms on 1.7 GHz processor).

With the fix applied the tsc delta reduced to 17740-29663 (wich translates to 9-17 us).

on v2:
 * replace compiler barrier with rte_io_wmb.

Shahaf Shuler (2):
  net/mlx5: replace memory barrier type
  net/mlx5: don't map doorbell register to write combining

Series applied to dpdk-next-net/master, thanks.