[PATCH 2/2] dmaengine: fsl-edma: add per-channel IOMMU support via iommu-map

@@ -283,8 +283,10 @@ int fsl_edma_resume(struct dma_chan *chan)
 
 static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan)
 {
+	struct device *dev = dmaengine_get_dma_device(&fsl_chan->vchan.chan);
+
 	if (fsl_chan->dma_dir != DMA_NONE)
-		dma_unmap_resource(fsl_chan->vchan.chan.device->dev,
+		dma_unmap_resource(dev,
 				   fsl_chan->dma_dev_addr,
 				   fsl_chan->dma_dev_size,
 				   fsl_chan->dma_dir, 0);

@@ -294,7 +296,7 @@ static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan)
 static bool fsl_edma_prep_slave_dma(struct fsl_edma_chan *fsl_chan,
 				    enum dma_transfer_direction dir)
 {
-	struct device *dev = fsl_chan->vchan.chan.device->dev;
+	struct device *dev = dmaengine_get_dma_device(&fsl_chan->vchan.chan);
 	enum dma_data_direction dma_dir;
 	phys_addr_t addr = 0;
 	u32 size = 0;

@@ -264,6 +264,7 @@ struct fsl_edma_engine {
 	int			txirq_16_31;
 	int			errirq;
 	bool			big_endian;
+	bool			has_iommu_map;
 	struct edma_regs	regs;
 	u64			chan_masked;
 	struct fsl_edma_chan	chans[] __counted_by(n_chans);

@@ -16,6 +16,7 @@
 #include <linux/interrupt.h>
 #include <linux/clk.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/of_dma.h>
 #include <linux/dma-mapping.h>
 #include <linux/pm_runtime.h>

@@ -24,6 +25,7 @@
 
 #include "fsl-edma-common.h"
 
+static int fsl_edma_chan_configure_iommu(struct fsl_edma_chan *fsl_chan);
 static void fsl_edma_synchronize(struct dma_chan *chan)
 {
 	struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);

@@ -298,7 +300,7 @@ static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
 	struct dma_chan *chan, *_chan;
 	struct fsl_edma_chan *fsl_chan;
 	bool b_chmux;
-	int i;
+	int i, ret;
 
 	if (dma_spec->args_count != 3)
 		return NULL;

@@ -332,6 +334,12 @@ static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
 		fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE;
 		fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO;
 
+		if (fsl_edma->has_iommu_map) {
+			ret = fsl_edma_chan_configure_iommu(fsl_chan);
+			if (ret)
+				return NULL;
+		}
+
 		chan = dma_get_slave_channel(chan);
 		chan->device->privatecnt++;
 		return chan;

@@ -695,6 +703,70 @@ static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_eng
 	return -EINVAL;
 }
 
+/**
+ * fsl_edma_init_chan_iommu - prepare per-channel devices for IOMMU
+ * @pdev: the eDMA platform device
+ * @fsl_edma: the eDMA engine instance
+ *
+ * Must be called after dmaenginem_async_device_register() so that each
+ * channel's chan->dev->device is already registered.
+ *
+ * Initialize DMA mask and bus on each channel device so that
+ * of_dma_configure_id() can be called later at xlate time.
+ */
+static void fsl_edma_init_chan_iommu(struct platform_device *pdev,
+				    struct fsl_edma_engine *fsl_edma)
+{
+	int i;
+
+	if (!of_property_present(pdev->dev.of_node, "iommu-map"))
+		return;
+
+	for (i = 0; i < fsl_edma->n_chans; i++) {
+		struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
+		struct device *dev;
+
+		if (fsl_edma->chan_masked & BIT(i))
+			continue;
+
+		dev = &fsl_chan->vchan.chan.dev->device;
+		dev->coherent_dma_mask = pdev->dev.coherent_dma_mask;
+		dev->dma_mask = &dev->coherent_dma_mask;
+		dev->bus = pdev->dev.bus;
+	}
+
+	fsl_edma->has_iommu_map = true;
+}
+
+static int fsl_edma_chan_configure_iommu(struct fsl_edma_chan *fsl_chan)
+{
+	struct device *dev = &fsl_chan->vchan.chan.dev->device;
+	struct device_node *np = fsl_chan->edma->dma_dev.dev->of_node;
+	struct of_phandle_args iommu_spec = {};
+	u32 chan_id = fsl_chan - fsl_chan->edma->chans;
+	int ret;
+
+	if (fsl_chan->vchan.chan.dev->chan_dma_dev)
+		return 0;
+
+	ret = of_map_iommu_id(np, chan_id, &iommu_spec);
+	if (ret || !iommu_spec.np)
+		return 0;
+	of_node_put(iommu_spec.np);
+
+	ret = of_dma_configure_id(dev, np, true, &chan_id);
+	if (ret) {
+		dev_err(dev, "DMA configure failed for ch%u: %d\n",
+			chan_id, ret);
+		return ret;
+	}
+
+	fsl_chan->vchan.chan.dev->chan_dma_dev = true;
+	dev_dbg(dev, "ch%u: IOMMU domain configured\n", chan_id);
+
+	return 0;
+}
+
 static int fsl_edma_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;

@@ -882,6 +954,8 @@ static int fsl_edma_probe(struct platform_device *pdev)
 		return dev_err_probe(&pdev->dev, ret,
 				     "Can't register Freescale eDMA engine.\n");
 
+	fsl_edma_init_chan_iommu(pdev, fsl_edma);
+
 	ret = devm_of_dma_controller_register(&pdev->dev, np,
 			drvdata->dmamuxs ? fsl_edma_xlate : fsl_edma3_xlate,
 			fsl_edma);