[PATCH 3/8] soc: renesas: rzn1-sysc: Export function to set dmamux
From: Miquel Raynal <miquel.raynal@bootlin.com>
Date: 2022-02-18 18:12:39
Also in:
linux-clk, linux-devicetree, linux-renesas-soc
Subsystem:
arm/risc-v/renesas architecture, common clk framework, open firmware and flattened device tree bindings, renesas clock drivers, the rest · Maintainers:
Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
The dmamux register is located within the system controller. Without syscon, we need an extra helper in order to give write access to this register to a dmamux driver. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/clk/renesas/r9a06g032-clocks.c | 27 +++++++++++++++++++ include/dt-bindings/clock/r9a06g032-sysctrl.h | 2 ++ include/linux/soc/renesas/r9a06g032-syscon.h | 11 ++++++++ 3 files changed, 40 insertions(+) create mode 100644 include/linux/soc/renesas/r9a06g032-syscon.h
diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index c99942f0e4d4..3bca60fac21c 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c@@ -315,6 +315,27 @@ struct r9a06g032_priv { void __iomem *reg; }; +/* Exported helper to access the DMAMUX register */ +static struct r9a06g032_priv *syscon_priv; +int r9a06g032_syscon_set_dmamux(u32 mask, u32 val) +{ + u32 dmamux; + + if (!syscon_priv) + return -EPROBE_DEFER; + + spin_lock(&syscon_priv->lock); + + dmamux = readl(syscon_priv->reg + R9A06G032_SYSCON_DMAMUX); + dmamux &= ~mask; + dmamux |= val & mask; + writel(dmamux, syscon_priv->reg + R9A06G032_SYSCON_DMAMUX); + + spin_unlock(&syscon_priv->lock); + + return 0; +} + /* register/bit pairs are encoded as an uint16_t */ static void clk_rdesc_set(struct r9a06g032_priv *clocks,
@@ -922,6 +943,12 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev) clocks->reg = of_iomap(np, 0); if (WARN_ON(!clocks->reg)) return -ENOMEM; + + if (syscon_priv) + return -EBUSY; + + syscon_priv = clocks; + for (i = 0; i < ARRAY_SIZE(r9a06g032_clocks); ++i) { const struct r9a06g032_clkdesc *d = &r9a06g032_clocks[i]; const char *parent_name = d->source ?
diff --git a/include/dt-bindings/clock/r9a06g032-sysctrl.h b/include/dt-bindings/clock/r9a06g032-sysctrl.h
index 90c0f3dc1ba1..609e7fe8fcb1 100644
--- a/include/dt-bindings/clock/r9a06g032-sysctrl.h
+++ b/include/dt-bindings/clock/r9a06g032-sysctrl.h@@ -145,4 +145,6 @@ #define R9A06G032_CLK_UART6 152 #define R9A06G032_CLK_UART7 153 +#define R9A06G032_SYSCON_DMAMUX 0xA0 + #endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */
diff --git a/include/linux/soc/renesas/r9a06g032-syscon.h b/include/linux/soc/renesas/r9a06g032-syscon.h
new file mode 100644
index 000000000000..d97e0e91cc6a
--- /dev/null
+++ b/include/linux/soc/renesas/r9a06g032-syscon.h@@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_SOC_RENESAS_R9A06G032_SYSCON_H__ +#define __LINUX_SOC_RENESAS_R9A06G032_SYSCON_H__ + +#ifdef CONFIG_CLK_R9A06G032 +int r9a06g032_syscon_set_dmamux(u32 mask, u32 val); +#else +static inline int r9a06g032_syscon_set_dmamux(u32 mask, u32 val) { return -ENODEV; } +#endif + +#endif /* __LINUX_SOC_RENESAS_R9A06G032_SYSCON_H__ */
--
2.27.0