[PATCH v3 05/15] clk: socfpga: build together Stratix 10, Agilex and N5X clock drivers
From: Krzysztof Kozlowski <hidden>
Date: 2021-03-11 15:27:07
Also in:
linux-arm-kernel, linux-clk, linux-devicetree, linux-edac, linux-fpga, linux-i2c, lkml, netdev
Subsystem:
arm/socfpga clock framework support, common clk framework, the rest · Maintainers:
Dinh Nguyen, Michael Turquette, Stephen Boyd, Linus Torvalds
On a multiplatform kernel there is little benefit in splitting each clock driver per platform because space savings are minimal. Such split also complicates the code, especially after adding compile testing. Build all arm64 Intel SoCFPGA clocks together with one entry in Makefile. This also removed duplicated line in the Makefile (selecting common part of clocks per platform). Signed-off-by: Krzysztof Kozlowski <redacted> --- drivers/clk/socfpga/Kconfig | 6 +++--- drivers/clk/socfpga/Makefile | 7 +++---- 2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig
index 3c30617169bf..bc102e0f0be0 100644
--- a/drivers/clk/socfpga/Kconfig
+++ b/drivers/clk/socfpga/Kconfig@@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 config CLK_INTEL_SOCFPGA64 bool - # Intel Agilex / N5X clock controller support - default (ARCH_AGILEX || ARCH_N5X) - depends on ARCH_AGILEX || ARCH_N5X + # Intel Stratix / Agilex / N5X clock controller support + default (ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10) + depends on ARCH_AGILEX || ARCH_N5X || ARCH_STRATIX10
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index c6db8dd4ab35..ebd3538d12de 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile@@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o -obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o -obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o -obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-agilex.o -obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o +obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \ + clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \ + clk-agilex.o
--
2.25.1