On Wed, Jan 6, 2021 at 2:25 AM EastL [off-list ref] wrote:

On Sun, 2021-01-03 at 09:58 -0700, Rob Herring wrote:

quoted

On Wed, Dec 23, 2020 at 05:30:44PM +0800, EastL Lee wrote:

quoted

Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6779 SoC or other similar Mediatek SoCs.

Signed-off-by: EastL Lee <redacted>
---
 .../devicetree/bindings/dma/mtk-cqdma.yaml         | 104 +++++++++++++++++++++

Use compatible string for filename:

OK

quoted

mediatek,cqdma.yaml

quoted

 1 file changed, 104 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml

diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
new file mode 100644
index 0000000..a76a263
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml

@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml#

Don't forget to update this.

OK

quoted

quoted

+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Command-Queue DMA controller Device Tree Binding
+
+maintainers:
+  - EastL Lee [off-list ref]
+
+description:
+  MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC
+  is dedicated to memory-to-memory transfer through queue based
+  descriptor management.
+
+allOf:
+  - $ref: "dma-controller.yaml#"
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt6765-cqdma
+          - mediatek,mt6779-cqdma
+      - const: mediatek,cqdma
+
+  reg:
+    minItems: 1
+    maxItems: 5
+    description:
+        A base address of MediaTek Command-Queue DMA controller,
+        a channel will have a set of base address.
+
+  interrupts:
+    minItems: 1
+    maxItems: 5
+    description:
+        A interrupt number of MediaTek Command-Queue DMA controller,
+        one interrupt number per dma-channels.
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: cqdma
+
+  dma-channel-mask:
+    description:
+       For DMA capability, We will know the addressing capability of
+       MediaTek Command-Queue DMA controller through dma-channel-mask.
+      minimum: 1
+      maximum: 63

Indentation is wrong here so this has no effect.

I'll fix it

quoted

A mask of 63 is 6 channels...

In my opinion, kernel dma mask if for 32/64 bit capability...
If I don't set dma mask I will get fail on DMATEST.

As in the kernel's 'dma_mask'? That's something entirely different.
The driver should set the mask to the max the device supports.
Typically this is a 32-bit or 64-bit mask. The default is 32-bit. If
the SoC has limitations in its buses, then you need to use
'dma-ranges' in DT which will in turn set the bus_dma_limit.

For the above, the purpose is if you have sparsely allocated DMA channels.

Rob