On Mon, Aug 27, 2018 at 7:31 AM Vinod [off-list ref] wrote:

On 02-08-18, 16:10, Andrea Merello wrote:

quoted

The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add DOC for it.

Add Documentation for it...

OK

quoted

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Radhey Shyam Pandey <redacted>
Signed-off-by: Andrea Merello <redacted>
Reviewed-by: Radhey Shyam Pandey <redacted>
---
Changes in v2:
      - change property name
      - property is now optional
      - cc DT maintainer
Changes in v3:
      - reword
      - cc DT maintainerS and ML
Changes in v4:
      - specify the unit, the valid range and the default value
---
 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index a2b8bfaec43c..aec4a41a03ae 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt

@@ -41,6 +41,10 @@ Optional properties:
 - xlnx,include-sg: Tells configured for Scatter-mode in
      the hardware.
 Optional properties for AXI DMA:
+- xlnx,sg-length-width: Should be set to the width in bits of the length
+     register as configured in h/w. Takes values {8...26}. If the property
+     is missing or invalid then the default value 23 is used. This is the
+     maximum value that is supported by all IP versions.
 - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
 Optional properties for VDMA:
 - xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
--

2.17.1

--
~Vinod