The MIO DMAC (Media IO DMA Controller) is used in UniPhier LD4,
Pro4, and sLD8 SoCs.

Signed-off-by: Masahiro Yamada <redacted>
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 .../devicetree/bindings/dma/uniphier-mio-dmac.txt  | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt

diff --git a/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt b/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt
new file mode 100644
index 0000000..a9e969e
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt

@@ -0,0 +1,28 @@
+UniPhier Media IO DMA controller
+
+This works as an external DMA engine for SD/eMMC controllers etc.
+found in UniPhier LD4, Pro4, sLD8 SoCs.
+
+Required properties:
+- compatible: should be "socionext,uniphier-mio-dmac".
+- reg: offset and length of the register set for the device.
+- interrupts: a list of interrupt specifiers associated with the DMA channels.
+- clocks: a single clock specifier
+- #dma-cells: should be <1>. The single cell represents the channel number.
+- dma-channels: specify the number of the DMA channels. This should match to
+  the number of tuples in the interrupts property.
+
+Example:
+       dmac: dmac@5a000000 {
+               compatible = "socionext,uniphier-mio-dmac";
+               reg = <0x5a000000 0x1000>;
+               interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
+                            <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
+               clocks = <&mio_clk 7>;
+               #dma-cells = <1>;
+               dma-channels = <8>;
+       };
+
+Note:
+In the example above, "interrupts = <0 68 4>, <0 68 4>, ..." is not a typo.
+The first two channels share a single interrupt line.
--

2.7.4