[PATCH AUTOSEL 5.12 078/160] drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7
From: Sasha Levin <sashal@kernel.org>
Date: 2021-07-06 11:35:23
Also in:
amd-gfx, dri-devel, lkml
Subsystem:
amd display core, drm drivers, radeon and amdgpu drm drivers, the rest · Maintainers:
Harry Wentland, Leo Li, David Airlie, Simona Vetter, Alex Deucher, Christian König, Linus Torvalds
From: Wesley Chalmers <redacted> [ Upstream commit 3577e1678772ce3ede92af3a75b44a4b76f9b4ad ] [WHY] DISPCLK_MAX_ERRDET_CYCLES must be 7 to prevent connection loss when changing DENTIST_DISPCLK_WDIVIDER from 126 to 127 and back. Signed-off-by: Wesley Chalmers <redacted> Reviewed-by: Dmytro Laktyushkin <redacted> Acked-by: Stylon Wang <redacted> Tested-by: Daniel Wheeler <redacted> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index aece1103331d..d8a03d825623 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c@@ -243,7 +243,7 @@ void dcn20_dccg_init(struct dce_hwseq *hws) REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); /* This value is dependent on the hardware pipeline delay so set once per SOC */ - REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c); + REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); } void dcn20_disable_vga(
--
2.30.2