https://go-review.googlesource.com/c/go/+/239217
https://go-review.googlesource.com/c/go/+/237058

v3->v4:
        introduce a config option: CONFIG_MIPS_O32_FPXX_USE_FR0

v2->v3:
        commit message: add Signed-off-by and Cc to stable.

v1->v2:
        Fix bad commit message: in fact, we are switching to FR=0

Signed-off-by: YunQiang Su <redacted>
Cc: stable@vger.kernel.org # 4.19+
---
 arch/mips/Kconfig      | 11 +++++++++++
 arch/mips/kernel/elf.c | 13 ++++++++++---
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 0a17bedf4f0d..442db620636f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig

@@ -3100,6 +3100,17 @@ config MIPS_O32_FP64_SUPPORT

          If unsure, say N.

+config MIPS_O32_FPXX_USE_FR0
+       bool "Use FR=0 mode for O32 FPXX binaries" if !CPU_MIPSR6
+       depends on MIPS_O32_FP64_SUPPORT
+       help
+         O32 FPXX can works on both FR=0 and FR=1 mode, so by default, the
+         mode preferred by hardware is used.
+
+         While some binaries may be marked as FPXX by mistake, for example
+         output of golang: they are in fact FP32 mode. To compatiable with
+         these binaries, we should use FR=0 mode for them.
+
 config USE_OF
        bool
        select OF

diff --git a/arch/mips/kernel/elf.c b/arch/mips/kernel/elf.c
index 7b045d2a0b51..443ced26ee60 100644
--- a/arch/mips/kernel/elf.c
+++ b/arch/mips/kernel/elf.c

@@ -234,9 +234,10 @@ int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr,
         *   fpxx case. This is because, in any-ABI (or no-ABI) we have no FPU
         *   instructions so we don't care about the mode. We will simply use
         *   the one preferred by the hardware. In fpxx case, that ABI can
-        *   handle both FR=1 and FR=0, so, again, we simply choose the one
-        *   preferred by the hardware. Next, if we only use single-precision
-        *   FPU instructions, and the default ABI FPU mode is not good
+        *   handle both FR=1 and FR=0. Here, we may need to use FR=0, because
+        *   some binaries may be mark as FPXX by mistake (ie, output of golang).
+        * - If we only use single-precision FPU instructions,
+        *   and the default ABI FPU mode is not good
         *   (ie single + any ABI combination), we set again the FPU mode to the
         *   one is preferred by the hardware. Next, if we know that the code
         *   will only use single-precision instructions, shown by single being

@@ -248,8 +249,14 @@ int arch_check_elf(void *_ehdr, bool has_interpreter, void *_interp_ehdr,
         */
        if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1)
                state->overall_fp_mode = FP_FRE;
+#if CONFIG_MIPS_O32_FPXX_USE_FR0
+       else if (prog_req.fr1 && prog_req.frdefault)
+               state->overall_fp_mode = FP_FR0;
+       else if (prog_req.single && !prog_req.frdefault)
+#else
        else if ((prog_req.fr1 && prog_req.frdefault) ||
                 (prog_req.single && !prog_req.frdefault))
+#endif
                /* Make sure 64-bit MIPS III/IV/64R1 will not pick FR1 */
                state->overall_fp_mode = ((raw_current_cpu_data.fpu_id & MIPS_FPIR_F64) &&
                                          cpu_has_mips_r2_r6) ?
--

2.20.1