quoted
We need to understand this, because if it is an RGMII PHY, we need to
address the RGMII delays, which that page says it can controller.
That part I still have to find out. My driver has always told phylib
gmii and the WAN port runs at 1 Gbs, but I have not worked out yet
what the link between the SoC and the ZX5201 really is.
https://www.sanechips.com.cn/en/Products/WiredEn/fixedNetworkTerminalEn/1558027080778723330.html
This says it is RGMII.
SerDes was just the name I gave the registers at the second address,
and there is no public documentation for them. I will find out what
the interface is, and how the delays are set if it is RGMII, before
I send the networking patches again.
So picking SERDES is probably causing some of this confusion. SERDES
implies there is a PCS, and the PCS is doing signalling for SGMII or
1000BaseX. With RGMII, none of that exists. The registers might be
controlling clocks, or regulators etc.
https://www.sanechips.com.cn/en/ProductEn/WiredEn/ethernetConnectivityEn/index.html
Also says RGMII.
Andrew