When the 5720 was linked up at 1G, it may fail to wake up on a
single Magic packet. This is a hardware issue, which can be avoided
by locking the PLL clock source before shutdown.
When preparing for power down with Wake-on-LAN enabled, if the link was
up at 1G, set CPMU_PLL_TLP_CLCK_SRC_NCSI_PLL in TG3_CPMU_PLL_CTRL_STAT,
so that the NCSI PLL locks on the TLP clock. The setting is cleared on
the next chip reset.
This was reported by a user, who confirmed that this change fixes it.
Fixes: ba1f3c76d760 ("tg3: Enable 5720 support")
Reviewed-by: Somnath Kotur <redacted>
Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: Pavan Chebbi <pavan.chebbi@broadcom.com>
---
drivers/net/ethernet/broadcom/tg3.c | 14 ++++++++++++++
drivers/net/ethernet/broadcom/tg3.h | 6 +++++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 2cf9d2ea069b..e9b48e58fdd4 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -4127,6 +4127,14 @@ static void tg3_power_down_prepare(struct tg3 *tp)
if (device_should_wake) {
u32 mac_mode;
+ if (tg3_asic_rev(tp) == ASIC_REV_5720 &&
+ tp->link_config.active_speed == SPEED_1000) {
+ u32 val = tr32(TG3_CPMU_PLL_CTRL_STAT);
+
+ tw32(TG3_CPMU_PLL_CTRL_STAT,
+ val | CPMU_PLL_TLP_CLCK_SRC_NCSI_PLL);
+ }
+
if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
if (do_low_power &&
!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {@@ -9394,6 +9402,12 @@ static int tg3_chip_reset(struct tg3 *tp)
tg3_restore_clk(tp);
+ if (tg3_asic_rev(tp) == ASIC_REV_5720) {
+ val = tr32(TG3_CPMU_PLL_CTRL_STAT);
+ tw32(TG3_CPMU_PLL_CTRL_STAT,
+ val & ~CPMU_PLL_TLP_CLCK_SRC_NCSI_PLL);
+ }
+
/* Increase the core clock speed to fix tx timeout issue for 5762
* with 100Mbps link speed.
*/diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
index a9e7f88fa26d..631bacc515ab 100644
--- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -1168,7 +1168,11 @@
#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
#define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
#define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
-/* 0x3634 --> 0x365c unused */
+/* 0x3634 unused */
+
+#define TG3_CPMU_PLL_CTRL_STAT 0x00003638
+#define CPMU_PLL_TLP_CLCK_SRC_NCSI_PLL 0x04000000
+/* 0x363c --> 0x365c unused */
#define TG3_CPMU_MUTEX_REQ 0x0000365c
#define CPMU_MUTEX_REQ_DRIVER 0x00001000
--
2.52.0