On Wed, Nov 4, 2026 at 12:36 AM Mieczyslaw Nalewaj [off-list ref] wrote:
The L2 lookup table on family D switches (e.g. RTL8367S-VB) differs
from family C in ways that make the current FDB/MDB code misbehave:
- An L2 entry is 5 words instead of 6, with a different field layout
in words 3 and 4 (port, age, static and multicast member bits).
- There is no EFID and no per-bridge FDB isolation. The register at
0x0A32, used as the per-port EFID register on family C, is the LUT
aging timer on family D, so writing an EFID there corrupts it.
- In the table access interface, the SPA field is 3 bits wide and the
address register is 12 bits wide, with no address extension bit.
- Only ports 0..7 are present in the LUT and there is no
FLUSH_PORT_EXT register.
Teach the table and L2 code about these differences, selecting the
layout at runtime with rtl8365mb_is_d(). Family C behavior is
unchanged.
Specifically:
- rtl8365mb_table: use the family D port mask and address width, and
read the hit address from status bits [11:0].
- rtl8365mb_l2: add family D unicast/multicast entry (de)serializers
and dispatch to them from the rtl8365mb_l2_*() helpers, pass the
proper entry size to the table layer, reject ports above 7, report
SVL (FID) entries with VID 0. Use age 6 for static unicast entries
as the vendor code does, and look an entry up before deleting it so
that a missing entry is not allocated by the delete.
- rtl8365mb_main: make port_set_efid() a no-op on family D, add a LUT
init step that clears IPMC_HASH and BCAM_DISABLE and programs the
aging timer, and do not advertise fdb_isolation or
max_num_bridges. Traffic between bridges is then isolated by the
port isolation masks only.
Register layouts were taken from the family D register description;
the code itself is an independent implementation.
No chip uses family D before the last patch of the series, so this code
is unreachable until then.
Signed-off-by: Mieczyslaw Nalewaj <redacted>
LGTM
Reviewed-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij