[PATCH net-next] net/stmmac/dwxgmac: Extend MTL/DMA support to 16 queues

From: Jakub Raczynski <redacted>

New datasheets for XGMAC (3.20a and 3.40a, depending on product)
support up to 16 MTL/DMA queues. Before we increase max amount
through macro, prepare dwxgmac functions to handle that.

Queue numbers above 15 are not valid for this hardware. Callers are
expected to bound them, so reaching the default case is a programming
error rather than a runtime condition. Use WARN_ON() for it instead
of a netdev_err() message: the callback has no net_device of its own,
and a message-only failure in a void callback is easy to miss, while a
warning with a backtrace points straight at the offending caller.

Co-developed-by: Chang-Sub Lee <redacted>
Signed-off-by: Chang-Sub Lee <redacted>
Signed-off-by: Jakub Raczynski <redacted>
Co-developed-by: Sagar Cheluvegowda <redacted>
Signed-off-by: Sagar Cheluvegowda <redacted>
---
Patch 2/3 of Jakub's v2 series:
https://lore.kernel.org/netdev/20260601162537.553512-3-j.raczynski@samsung.com/ (local)

Jakub has confirmed he will not be continuing this series, so we are
posting this patch on its own. We need it for Qualcomm Nord, a
25GMAC-based SoC that implements 12 MTL/DMA queues. Jakub's authorship
and sign-offs are kept.

Changes vs v2 2/3:
- Replace the netdev_err() + return in the default case with
  WARN_ON() + return, following the review feedback on 1/3 against
  message-only failures in void callbacks.

Tested on Qualcomm Nord with 12 queues: the MAP0..MAP2 registers were
checked to hold the expected RX queue to DMA channel mapping. The MAP3
register (queues 12-15) is carried over unchanged from v2 and is not
exercised on that hardware.

This is needed for XGMAC-based hardware with more than 8 MTL/DMA
queues (Qualcomm Nord has 12).

 .../net/ethernet/stmicro/stmmac/dwxgmac2.h    |  2 ++
 .../ethernet/stmicro/stmmac/dwxgmac2_core.c   | 21 +++++++++++++++++--
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index f8ab347f7b5b..6d4affbd34a1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h

@@ -257,6 +257,8 @@
 #define XGMAC_MTL_INT_STATUS		0x00001020
 #define XGMAC_MTL_RXQ_DMA_MAP0		0x00001030
 #define XGMAC_MTL_RXQ_DMA_MAP1		0x00001034
+#define XGMAC_MTL_RXQ_DMA_MAP2		0x00001038
+#define XGMAC_MTL_RXQ_DMA_MAP3		0x0000103c
 #define XGMAC_QxMDMACH(x)		GENMASK((x) * 8 + 7, (x) * 8)
 #define XGMAC_QxMDMACH_SHIFT(x)		((x) * 8)
 #define XGMAC_QDDMACH			BIT(7)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
index 1a88cbaed70c..563d29d72543 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c

@@ -257,9 +257,26 @@ static void dwxgmac2_map_mtl_to_dma(struct mac_device_info *hw, u32 queue,
 	void __iomem *ioaddr = hw->pcsr;
 	u32 value, reg;
 
-	reg = (queue < 4) ? XGMAC_MTL_RXQ_DMA_MAP0 : XGMAC_MTL_RXQ_DMA_MAP1;
-	if (queue >= 4)
+	switch (queue) {
+	case 0 ... 3:
+		reg = XGMAC_MTL_RXQ_DMA_MAP0;
+		break;
+	case 4 ... 7:
+		reg = XGMAC_MTL_RXQ_DMA_MAP1;
 		queue -= 4;
+		break;
+	case 8 ... 11:
+		reg = XGMAC_MTL_RXQ_DMA_MAP2;
+		queue -= 8;
+		break;
+	case 12 ... 15:
+		reg = XGMAC_MTL_RXQ_DMA_MAP3;
+		queue -= 12;
+		break;
+	default:
+		WARN_ON(1);
+		return;
+	}
 
 	value = readl(ioaddr + reg);
 	value &= ~XGMAC_QxMDMACH(queue);

-- 
2.34.1