Re: [PATCH net-next v13 02/12] dt-bindings: dpll: add SiTime SiT95316 clock generator

Add a binding for the SiTime SiT9531x family of clock generators: an
I2C-controlled device with four independent PLLs, up to eight input
clocks and up to twelve outputs, described as a DPLL provider.

The XO is given either as a clock or, for firmware that describes the
oscillator as a property rather than as a clock provider, such as ACPI,
as clock-frequency.

The supplies are described by their pin names: the core and input rails,
the GPIO rail the SiT95317 has, and one per output-driver pin -- VDDO0 to
VDDO7 on the SiT95317, VDDO0_1, VDDO2 to VDDO9 and VDDO10_11 on the
SiT95316.  The driver does not enable them, since the boards so far
power the part permanently; describing them gives a board with
switchable rails a way to say so.

Signed-off-by: Ali Rouhi <redacted>
---
 .../bindings/dpll/sitime,sit95316.yaml        | 213 ++++++++++++++++++
 MAINTAINERS                                   |   6 +
 2 files changed, 219 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml

diff --git a/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml b/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml
new file mode 100644
index 000000000000..200b9f709a57
--- /dev/null
+++ b/Documentation/devicetree/bindings/dpll/sitime,sit95316.yaml

@@ -0,0 +1,213 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dpll/sitime,sit95316.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiTime SiT95316/SiT95317 DPLL Clock Generator
+
+maintainers:
+  - Ali Rouhi <arouhi@sitime.com>
+
+description: |
+  SiTime SiT95316 and SiT95317 are I2C-controlled programmable clock
+  generators with integrated DPLL for synchronization applications.  Both
+  variants contain four PLLs with automatic/manual reference selection,
+  DCO frequency adjustment, and phase offset measurement via an on-chip
+  TDC (Time-to-Digital Converter).
+
+  Both parts have 4 differential input pairs whose lanes can also be
+  driven independently as single-ended references, so 8 inputs are
+  individually selectable.  SiT95317 drives 8 outputs, SiT95316
+  drives 12.
+
+  Pin numbering.  An input pin's reg is its lane: 2k is INkP and 2k + 1
+  is INkN, 0 to 7.  A pair the loaded configuration runs differential is
+  one input, described at 2k.  An output pin's reg is its physical output
+  OUTn, 0 to 11; the SiT95317 bonds out OUT0, OUT3, OUT4, OUT5, OUT7, OUT8,
+  OUT9 and OUT11.
+
+properties:
+  compatible:
+    enum:
+      - sitime,sit95316
+      - sitime,sit95317
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: xtal
+
+  clock-frequency:
+    description:
+      XO rate in Hz feeding XIN/XO_CLK, for firmware that describes the
+      oscillator as a property rather than as a clock provider, such as
+      ACPI.  Use either this or "clocks", not both.
+
+  reset-gpios:
+    maxItems: 1
+    description:
+      GPIO connected to the chip's active-low reset pin (RESETB).
+
+  interrupts:
+    maxItems: 1
+    description:
+      Interrupt from the chip's active-low INTRB output.  Asserted when
+      the device detects a status change such as lock acquisition or loss.
+
+  dpll-types:
+    maxItems: 4
+
+  vdd-supply:
+    description: Core supply of the PLLs, 1.8 V (the VDD pins).
+
+  vddin-supply:
+    description:
+      Supply of the input receivers and dividers, 3.3 V (VDDIN).
+
+  vdds-supply:
+    description:
+      Supply of the two GPIO pins that have their own rail (VDDS).  The
+      SiT95316 has no such pin.
+
+  input-pins:
+    type: object
+    patternProperties:
+      "^pin@[0-9a-f]+$":
+        type: object
+        properties:
+          reg:
+            maximum: 7
+
+          supported-frequencies-hz:
+            description:
+              The rate wired to the input, in Hz, as a single entry.  An
+              input runs at the rate the board feeds it and has no
+              frequency to select, so that entry is what the pin reports
+              as its frequency.
+
+patternProperties:
+  "^vddo([0-9]|1[01]|0_1|10_11)-supply$":
+    description: |
+      Supply of an output driver, named after its VDDO pin.  The SiT95317
+      has one per output, VDDO0 to VDDO7, numbered as that part's
+      datasheet numbers its outputs; in the pin numbering of this binding
+      those are outputs 0, 3, 4, 5, 7, 8, 9 and 11, in that order.  The
+      SiT95316 has VDDO0_1, VDDO2 to VDDO9 and VDDO10_11, the two shared
+      pins each powering the pair of outputs they are named after.
+
+required:
+  - compatible
+  - reg
+
+dependencies:
+  clocks: [ clock-names ]
+
+oneOf:
+  - required:
+      - clocks
+  - required:
+      - clock-frequency
+
+allOf:
+  - $ref: /schemas/dpll/dpll-device.yaml#
+  - if:
+      properties:
+        compatible:
+          const: sitime,sit95317
+    then:
+      properties:
+        output-pins:
+          patternProperties:
+            "^pin@[0-9a-f]+$":
+              properties:
+                reg:
+                  enum: [0, 3, 4, 5, 7, 8, 9, 11]
+      patternProperties:
+        "^vddo(8|9|1[01]|0_1|10_11)-supply$": false
+    else:
+      properties:
+        vdds-supply: false
+        output-pins:
+          patternProperties:
+            "^pin@[0-9a-f]+$":
+              properties:
+                reg:
+                  maximum: 11
+      patternProperties:
+        "^vddo(1[01]|[01])-supply$": false
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        dpll@68 {
+            compatible = "sitime,sit95316";
+            reg = <0x68>;
+            clocks = <&xo2>;
+            clock-names = "xtal";
+            reset-gpios = <&gpio 78 GPIO_ACTIVE_LOW>;
+            interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+            vdd-supply = <&reg_1v8>;
+            vddin-supply = <&reg_3v3>;
+            vddo0_1-supply = <&reg_3v3>;
+            vddo10_11-supply = <&reg_1v8>;
+            dpll-types = "eec", "eec", "eec", "eec";
+
+            input-pins {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                /* IN0P and IN0N: pair 0 runs single-ended */
+                pin@0 {
+                    reg = <0>;
+                    label = "clkin0";
+                    connection-type = "ext";
+                    supported-frequencies-hz = /bits/ 64 <10000000>;