[PATCH net-next v7 02/10] r8152: add new init writes for RTL8156/8156B/8157/8159
flat view
COOLING4d
From: Chih Kai Hsu <hidden>
Date: 2026-10-14 08:19:58
Also in:
linux-usb, lkml
Subsystem:
networking drivers, the rest, usb networking drivers · Maintainers:
Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
Revision v7 of 7 in this series.
Revisions (7)
Bring the per-generation init functions in line with the vendor init sequence by adding writes the shared r8156_init() never performed. - Clear PREBOOT_OPTION and RMT_WAKE_EN in r8156_init() and r8157_init(). - Add r8156b_u2phy_backup() for RTL8156B (VER_12/13/15). - Clear AUTO_SPEEDUP in r8157_init(). - Disable interrupt mitigation (0xcf04) in r8157_init(). - Clear the Warm RST / Bus RST event flag (0xcd06 BIT(11)) in r8157_init(). - Clear the FW u1u2 patch option (0xb9a6 BIT(0)) and enable the u3phy patch backup (0xb9a2) for RTL8159 (VER_17) only. - Clear RX_END_TRANSFER_EN (0xd406 BIT(11)) for RTL8157 (VER_16), too. While it is set, incoming packets are buffered in the RX FIFO and Bulk-in transfers are suspended. The bit is zero by default and isn't used now. Clear it unconditionally for safety. Signed-off-by: Chih Kai Hsu <redacted> --- drivers/net/usb/r8152.c | 77 ++++++++++++++++++++++++++++++++++------- 1 file changed, 64 insertions(+), 13 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index 518a2b42c2200..43a3f09b7c29b 100644
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb/r8152.c@@ -78,6 +78,7 @@ #define PLA_EEE_TXTWSYS_2P5G 0xe058 #define PLA_EEEP_CR 0xe080 #define PLA_MAC_PWR_CTRL 0xe0c0 +#define PLA_RMT_WAKE 0xe0c8 #define PLA_MAC_PWR_CTRL2 0xe0ca #define PLA_MAC_PWR_CTRL3 0xe0cc #define PLA_MAC_PWR_CTRL4 0xe0ce
@@ -371,6 +372,9 @@ #define MCU_CLK_RATIO_MASK 0x0f0f0f0f #define ALDPS_SPDWN_RATIO 0x0f87 +/* PLA_RMT_WAKE */ +#define RMT_WAKE_EN BIT(0) + /* PLA_MAC_PWR_CTRL2 */ #define EEE_SPDWN_RATIO 0x8007 #define MAC_CLK_SPDWN_EN BIT(15)
@@ -417,6 +421,7 @@ /* PLA_INDICATE_FALG */ #define UPCOMING_RUNTIME_D3 BIT(0) +#define PREBOOT_OPTION BIT(1) /* PLA_MACDBG_PRE and PLA_MACDBG_POST */ #define DEBUG_OE BIT(0)
@@ -542,6 +547,7 @@ #define RX_AGG_DISABLE 0x0010 #define RX_ZERO_EN 0x0080 #define RX_DESC_16B 0x0400 +#define RX_END_TRANSFER_EN BIT(11) /* USB_U2P3_CTRL */ #define U2P3_ENABLE 0x0001
@@ -8305,6 +8311,15 @@ static void r8157_hw_phy_cfg(struct r8152 *tp) set_bit(PHY_RESET, &tp->flags); } +static void r8156b_u2phy_backup(struct r8152 *tp) +{ + ocp_write_word(tp, MCU_TYPE_USB, 0xd3ce, 0x181b); + ocp_write_dword(tp, MCU_TYPE_USB, 0xd3d0, 0x616ccd99); + ocp_write_dword(tp, MCU_TYPE_USB, 0xd3d4, 0x08fc8101); + ocp_write_dword(tp, MCU_TYPE_USB, 0xd3d8, 0x159b1100); + ocp_write_word(tp, MCU_TYPE_USB, 0xd3dc, 0x0a00); +} + static void r8156_init(struct r8152 *tp) { u32 ocp_data;
@@ -8370,11 +8385,25 @@ static void r8156_init(struct r8152 *tp) /* U1/U2/L1 idle timer. 500 us */ ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); + switch (tp->version) { + case RTL_VER_12: + case RTL_VER_13: + case RTL_VER_15: + r8156b_u2phy_backup(tp); + break; + default: + break; + } + r8153b_power_cut_en(tp, false); r8156_ups_en(tp, false); r8153_queue_wake(tp, false); rtl_runtime_suspend_enable(tp, false); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, PREBOOT_OPTION); + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_RMT_WAKE, RMT_WAKE_EN); + if (tp->udev->speed >= USB_SPEED_SUPER) r8153b_u1u2en(tp, true);
@@ -8494,6 +8523,10 @@ static void r8157_init(struct r8152 *tp) r8157_u2p3en(tp, false); + /* Disable Interrupt Mitigation */ + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xcf04, + BIT(0) | BIT(1) | BIT(2) | BIT(7)); + /* MSC timer = 0xfff * 8ms = 32760 ms */ ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
@@ -8505,11 +8538,30 @@ static void r8157_init(struct r8152 *tp) r8153_queue_wake(tp, false); rtl_runtime_suspend_enable(tp, false); + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, PREBOOT_OPTION); + + ocp_byte_clr_bits(tp, MCU_TYPE_PLA, PLA_RMT_WAKE, RMT_WAKE_EN); + + /* Clear Warm RST / Bus RST event flag */ + ocp_word_clr_bits(tp, MCU_TYPE_USB, 0xcd06, BIT(11)); + + switch (tp->version) { + case RTL_VER_17: + /* Disable FW u1u2 patch option */ + ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xb9a6, BIT(0)); + break; + default: + break; + } + if (tp->udev->speed >= USB_SPEED_SUPER) r8153b_u1u2en(tp, true); usb_enable_lpm(tp->udev); + /* Disable Auto Speed up */ + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_FW_CTRL, AUTO_SPEEDUP); + r8156_mac_clk_spd(tp, true); if (rtl8152_get_speed(tp) & LINK_STATUS)
@@ -8521,19 +8573,9 @@ static void r8157_init(struct r8152 *tp) set_bit(GREEN_ETHERNET, &tp->flags); - /* RX aggregation / 16 bytes RX descriptor - * BIT(11) is specific to RTL8159, with unknown meaning - */ - switch (tp->version) { - case RTL_VER_17: - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, - RX_AGG_DISABLE | RX_DESC_16B | BIT(11)); - break; - default: - ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, - RX_AGG_DISABLE | RX_DESC_16B); - break; - } + /* RX aggregation / 16 bytes RX descriptor / Bulk In End transfer */ + ocp_word_clr_bits(tp, MCU_TYPE_USB, USB_USB_CTRL, + RX_AGG_DISABLE | RX_DESC_16B | RX_END_TRANSFER_EN); /* Disable Rx Zero Len */ rtl_bmu_clr_bits(tp, 0x2300, BIT(3));
@@ -8541,6 +8583,15 @@ static void r8157_init(struct r8152 *tp) /* TX descriptor Signature */ ocp_byte_clr_bits(tp, MCU_TYPE_USB, 0xd4ae, BIT(1)); + switch (tp->version) { + case RTL_VER_17: + /* Enable u3phy patch backup */ + ocp_write_word(tp, MCU_TYPE_USB, 0xb9a2, 0x0448); + break; + default: + break; + } + r8156_mdio_force_mode(tp); rtl_tally_reset(tp);
--
2.34.1