Re: [PATCH net-next v12 11/12] dpll: sit9531x: add support to get phase offset on the connected input pin

On 10/9/26 20:31, Ali Rouhi wrote:

From: Oleg Zadorozhnyi <redacted>

Report the phase difference between a PLL's reference and the PLL itself,
which is the loop's own residual error and therefore trends small on a
locked device -- that is the measurement, not an artefact of it.

The value comes from the on-chip time-to-digital converter, read through
the debug window: unlock the window, point it at the converter, then read
the trigger register, which latches a fresh sample and returns the
previous one.  It is read three times per sample for that reason; a single
read hands back the sample from the last call, so a repeated measurement
would look perfectly steady while saying nothing.  The offset keeps the
fraction of a picosecond the converter resolves.

Only the input the device feeds a PLL has a phase offset against it.
For any other pin there is nothing to measure and zero is reported,
because the core abandons an entire pin dump on an error from any one pin.
That pin reads zero too when no sample was taken: the PLL is not
tracking, drives no un-muted output, has no usable VCO rate, or the
device moved it off the pin, or the lane lost its signal, between the
check and the sample.

Signed-off-by: Oleg Zadorozhnyi <redacted>
Assisted-by: LLM
Signed-off-by: Ali Rouhi <redacted>
---

Reviewed-by: Ivan Vecera <ivecera@redhat.com>