[PATCH net-next v2 2/8] net: dsa: realtek: rtl8365mb: set speed for family D
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COLD16d
SUPERSEDED
From: Mieczyslaw Nalewaj <hidden>
Date: 2026-10-09 04:54:54
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lkml
Subsystem:
networking drivers, networking [dsa], realtek rtl83xx smi dsa router chips, the rest · Maintainers:
Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Andrew Lunn, Vladimir Oltean, Linus Walleij, Luiz Angelo Daros de Luca, Linus Torvalds
Status: Superseded by v6 (posted 2026-10-16). [go to v6]
Revision v2 (6 revisions archived).
Revisions (6)
On family C hardware, forcing a 2.5 Gbps link speed requires relying strictly on the HSGMII SerDes configuration block, while forcing a dummy 1 Gbps value inside the standard digital interface register. Family D introduces a dedicated hardware link speed value (5) for 2500M. The speed bitfield width has been expanded to 3 bits, splitting the most significant bit into a new separate register field (FORCE_SPEED2), which maps directly to a distinct per-port digital interface force layout. Signed-off-by: Mieczyslaw Nalewaj <redacted> --- drivers/net/dsa/realtek/rtl8365mb_main.c | 71 +++++++++++++++++++----- 1 file changed, 58 insertions(+), 13 deletions(-)
diff --git a/drivers/net/dsa/realtek/rtl8365mb_main.c b/drivers/net/dsa/realtek/rtl8365mb_main.c
index 80fc551..b1ea8b0 100644
--- a/drivers/net/dsa/realtek/rtl8365mb_main.c
+++ b/drivers/net/dsa/realtek/rtl8365mb_main.c@@ -346,6 +346,7 @@ #define RTL8365MB_PORT_SPEED_10M 0 #define RTL8365MB_PORT_SPEED_100M 1 #define RTL8365MB_PORT_SPEED_1000M 2 +#define RTL8365MB_D_PORT_SPEED_2500M 5 /* External interface force configuration registers 0~2 */ #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */
@@ -363,6 +364,20 @@ #define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK BIT(4) #define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK BIT(2) #define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK GENMASK(1, 0) +#define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_WIDTH 2 /* bits[1:0] */ + +/* bits[13:12]; bit 13 reserved, no defined speed value uses it yet */ +#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_SPEED2_MASK GENMASK(13, 12) + +#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG_BASE 0x12c0 +#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG(_port) \ + (RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG_BASE + (_port)) + +#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_EN_BASE 0x12c8 +#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG_EN(_port) \ + (RTL8365MB_D_DIGITAL_INTERFACE_FORCE_EN_BASE + (_port)) + +#define RTL8365MB_D_DIGITAL_INTERFACE_FORCE_EN_ALL_MASK GENMASK(15, 0) /* CPU port mask register - controls which ports are treated as CPU ports */ #define RTL8365MB_CPU_PORT_MASK_REG 0x1219
@@ -1661,23 +1676,31 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, u32 r_duplex; u32 r_speed; u32 r_link; + bool is_d; int val; int ret; if (!extint) return -ENODEV; + is_d = rtl8365mb_get_family(priv) == RTL8365MB_FAMILY_D; if (link) { /* Force the link up with the desired configuration */ r_link = 1; r_rx_pause = rx_pause ? 1 : 0; r_tx_pause = tx_pause ? 1 : 0; - /* The speed field has no value for 2.5 Gbps: the rate is - * determined by the HSGMII SerDes configuration, and the - * vendor driver programs the 1 Gbps value here. - */ - if (speed == SPEED_2500 || speed == SPEED_1000) { + if (speed == SPEED_2500) { + if (is_d) { + r_speed = RTL8365MB_D_PORT_SPEED_2500M; + } else { + /* The speed field has no value for 2.5 Gbps: the rate is + * determined by the HSGMII SerDes configuration, and the + * vendor driver programs the 1 Gbps value here. + */ + r_speed = RTL8365MB_PORT_SPEED_1000M; + } + } else if (speed == SPEED_1000) { r_speed = RTL8365MB_PORT_SPEED_1000M; } else if (speed == SPEED_100) { r_speed = RTL8365MB_PORT_SPEED_100M;
@@ -1707,20 +1730,42 @@ static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, r_duplex = 0; } - val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, + val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, r_tx_pause) | FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK, r_rx_pause) | FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) | FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, r_duplex) | - FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); - ret = regmap_write(priv->map, - RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id), - val); - if (ret) - return ret; + FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, + r_speed & RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK); + + if (is_d) { + /* Speed is 3 bits on family D: bits[1:0] go into FORCE_SPEED, + * bit[2] goes into FORCE_SPEED2 (bit 12); only 2500M sets it, + * bit 13 of the field is unused. + */ + val |= FIELD_PREP(RTL8365MB_D_DIGITAL_INTERFACE_FORCE_SPEED2_MASK, + r_speed >> RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_WIDTH); + ret = regmap_write(priv->map, + RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG(port), + val); + if (ret) + return ret; + + ret = regmap_write(priv->map, + RTL8365MB_D_DIGITAL_INTERFACE_FORCE_REG_EN(port), + RTL8365MB_D_DIGITAL_INTERFACE_FORCE_EN_ALL_MASK); + if (ret) + return ret; + } else { + val |= FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1); + ret = regmap_write(priv->map, + RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id), + val); + if (ret) + return ret; + } return 0; }
--
2.53.0