[PATCH v5 06/13] ARM: dts: imx6ul: Extend VAR-SOM-6UL and add DART-6UL files
flat view
COOLING4d
From: Stefano Radaelli <hidden>
Date: 2026-10-08 19:40:29
Also in:
imx, linux-arm-kernel, linux-devicetree, lkml
Subsystem:
arm/freescale imx / mxc / layerscape arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
From: Stefano Radaelli <redacted> Add the DART-6UL module description and wrappers for i.MX6UL, i.MX6ULL and i.MX6ULZ, plus an i.MX6ULZ wrapper for VAR-SOM-6UL. Extend the existing VAR-SOM-6UL files with CPU supplies, a 3.3 V ADC reference and I2C2 pin configuration with GPIO bus recovery. Enable I2C2 for the module codecs described in the following patch. Use iomuxc_snvs for the i.MX6ULL module's tamper pads. Describe the IW61x power-enable and reset pins on GPIO5_IO02 and GPIO5_IO06 separately from the Broadcom Wi-Fi and Bluetooth pin groups. Signed-off-by: Stefano Radaelli <redacted> --- v4->v5: - Clarify the title and description: extend the existing VAR-SOM-6UL support and add DART-6UL module files. - Extend imx6ul-var-som-common.dtsi and the existing SoC wrappers instead of replacing them. Keep the eMMC and I2C1 descriptions here until the patches that move them and update their consumers. - Retain the Broadcom pin groups and add a separate IW61x group with GPIO5_IO02 and GPIO5_IO06 matching the power-sequence pins. - Configure i.MX6ULL SNVS pads under iomuxc_snvs. v2->v3: - Constrain the fixed touch and ADC reference regulators to 3.3 V on both modules so the ADC can report a valid scale. .../dts/nxp/imx/imx6ul-imx6ull-var-dart.dtsi | 207 ++++++++++++++++++ .../arm/boot/dts/nxp/imx/imx6ul-var-dart.dtsi | 44 ++++ .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 38 ++++ arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 13 ++ .../boot/dts/nxp/imx/imx6ull-var-dart.dtsi | 44 ++++ .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 15 +- .../boot/dts/nxp/imx/imx6ulz-var-dart.dtsi | 51 +++++ .../arm/boot/dts/nxp/imx/imx6ulz-var-som.dtsi | 51 +++++ 8 files changed, 462 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-dart.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-dart.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-dart.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ulz-var-dart.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ulz-var-som.dtsi
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-dart.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-dart.dtsi
new file mode 100644
index 000000000000..f7190f6d50b5
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-imx6ull-var-dart.dtsi@@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com + */ + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + /* ref_clk for micrel ethernet phy */ + rmii_ref_clk: clock-rmii-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "rmii-ref"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_gpio_dvfs: regulator-gpio-dvfs { + compatible = "regulator-gpio"; + regulator-name = "gpio_dvfs"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-type = "voltage"; + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 + 1400000 0x0>; + }; + + touch_3v3_regulator: regulator-touch-3v3 { + compatible = "regulator-fixed"; + regulator-name = "touch_3v3_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + micrel,rmii-reference-clock-select-25-mhz = <1>; + micrel,led-mode = <1>; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +/* Bluetooth UART */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1-grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet1_mdio: enet1-mdio-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b0b0 + >; + }; + + pinctrl_tsc: tsc-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; +};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-dart.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-dart.dtsi
new file mode 100644
index 000000000000..eaac0455357d
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-dart.dtsi@@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-6UL + * + * Link: https://variscite.com/system-on-module-som/i-mx-6/i-mx-6ul/dart-6ul/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +#include "imx6ul-imx6ull-var-dart.dtsi" + +&adc1 { + vref-supply = <&touch_3v3_regulator>; + status = "okay"; +}; + +&iomuxc { + pinctrl_brcm_bt: brcm-bt-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON */ + >; + }; + + pinctrl_brcm_wifi: brcm-wifi-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON */ + >; + }; + + pinctrl_enet1_gpio: enet1-gpio-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 + >; + }; + + pinctrl_wifi: wifi-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 + >; + }; +};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
index 5600eeaa5854..9aab7c402f2c 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi@@ -5,6 +5,7 @@ * * Copyright 2019 Variscite Ltd. * Copyright 2025 Bootlin + * Copyright (C) 2026 Variscite Ltd. */ #include <dt-bindings/clock/imx6ul-clock.h>
@@ -37,6 +38,14 @@ reg_gpio_dvfs: reg-gpio-dvfs { states = <1300000 0x1 1400000 0x0>; }; + + touch_3v3_regulator: regulator-touch-3v3 { + compatible = "regulator-fixed"; + regulator-name = "touch_3v3_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; &clks {
@@ -44,6 +53,21 @@ &clks { assigned-clock-rates = <786432000>; }; +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + &iomuxc { pinctrl_i2c1: i2c1grp { fsl,pins = <
@@ -52,6 +76,20 @@ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 >; }; + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b0b0 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b0 + >; + }; + pinctrl_tsc: tscgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
index feea24c0e068..2936081749fb 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi@@ -4,6 +4,7 @@ * * Copyright 2019 Variscite Ltd. * Copyright 2025 Bootlin + * Copyright (C) 2026 Variscite Ltd. */ /dts-v1/;
@@ -16,6 +17,11 @@ / { compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; }; +&adc1 { + vref-supply = <&touch_3v3_regulator>; + status = "okay"; +}; + &iomuxc { pinctrl_brcm_bt: brcm-bt-grp { fsl,pins = <
@@ -35,4 +41,11 @@ pinctrl_enet1_gpio: enet1-gpiogrp { MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ >; }; + + pinctrl_wifi: wifi-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 + >; + }; };
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-dart.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-dart.dtsi
new file mode 100644
index 000000000000..4f8d570f5fe0
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-dart.dtsi@@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-6ULL + * + * Link: https://variscite.com/system-on-module-som/i-mx-6/i-mx-6ul/dart-6ul/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +#include "imx6ul-imx6ull-var-dart.dtsi" + +&adc1 { + vref-supply = <&touch_3v3_regulator>; + status = "okay"; +}; + +&iomuxc_snvs { + pinctrl_brcm_bt: brcm-bt-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON */ + >; + }; + + pinctrl_brcm_wifi: brcm-wifi-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR */ + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON */ + >; + }; + + pinctrl_enet1_gpio: enet1-gpio-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 + >; + }; + + pinctrl_wifi: wifi-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 + >; + }; +};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
index f120b1dca75c..ac41ffd353f6 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi@@ -4,6 +4,7 @@ * * Copyright 2019-2024 Variscite Ltd. * Copyright 2026 Dimonoff + * Copyright (C) 2026 Variscite Ltd. */ #include "imx6ull.dtsi"
@@ -14,7 +15,12 @@ / { compatible = "variscite,var-som-imx6ull", "fsl,imx6ull"; }; -&iomuxc { +&adc1 { + vref-supply = <&touch_3v3_regulator>; + status = "okay"; +}; + +&iomuxc_snvs { pinctrl_brcm_bt: brcm-bt-grp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON (BT_EN) */
@@ -33,4 +39,11 @@ pinctrl_enet1_gpio: enet1-gpiogrp { MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ >; }; + + pinctrl_wifi: wifi-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 + >; + }; };
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ulz-var-dart.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ulz-var-dart.dtsi
new file mode 100644
index 000000000000..b6a3518a3769
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ulz-var-dart.dtsi@@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-6ULZ + * + * Link: https://variscite.com/system-on-module-som/i-mx-6/i-mx-6ul/dart-6ul/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +#include "imx6ul-imx6ull-var-dart.dtsi" + +&fec1 { + status = "disabled"; +}; + +&pxp { + status = "disabled"; +}; + +&tsc { + status = "disabled"; +}; + +&iomuxc_snvs { + pinctrl_brcm_bt: brcm-bt-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON */ + >; + }; + + pinctrl_brcm_wifi: brcm-wifi-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR */ + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON */ + >; + }; + + pinctrl_enet1_gpio: enet1-gpio-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 + >; + }; + + pinctrl_wifi: wifi-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 + >; + }; +};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ulz-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ulz-var-som.dtsi
new file mode 100644
index 000000000000..01087cfd504a
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6ulz-var-som.dtsi@@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite VAR-SOM-6ULZ + * + * Link: https://variscite.com/system-on-module-som/i-mx-6/i-mx-6ul/var-som-6ul/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +#include "imx6ul-var-som-common.dtsi" + +&fec1 { + status = "disabled"; +}; + +&pxp { + status = "disabled"; +}; + +&tsc { + status = "disabled"; +}; + +&iomuxc_snvs { + pinctrl_brcm_bt: brcm-bt-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON */ + >; + }; + + pinctrl_brcm_wifi: brcm-wifi-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR */ + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON */ + >; + }; + + pinctrl_enet1_gpio: enet1-gpio-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 + >; + }; + + pinctrl_wifi: wifi-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 + >; + }; +};
--
2.47.3