[PATCH net-next v2] net: stmmac: dwxgmac2: enable L2 split header support
flat view
WARM3d
From: Sagar Cheluvegowda <hidden>
Date: 2026-10-07 18:39:21
Also in:
linux-arm-kernel, linux-arm-msm, lkml
Subsystem:
networking drivers, stmmac ethernet driver, the rest · Maintainers:
Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Maxime Chevallier, Linus Torvalds
XGMAC2 doesn't program the MAC extended configuration registers
needed for L2 header splitting when split-header mode is enabled,
so tagged AV packets can't use the split-header path. Configure
split mode (SPLM) and header saving (SAVE_EN) in XGMAC_EXT_CFG1,
extending the dwmac4 sequence added by commit d10f1a4e44c3 ("net:
stmmac: Programming sequence for VLAN packets with split header")
to XGMAC2.
Also fix the RX header-length calculation for split-header
descriptors. Per the XGMAC2 descriptor format, RDES3's L34T and
L2T fields are only valid on the last descriptor (LD set); on a
non-last descriptor they can hold stale write-back data from a
previous packet. Read the header length from RDES2[9:0] directly
for non-last descriptors, and only consult L34T/L2T on the last
descriptor: RDES2[9:0] for IP packets (L34T set) and RDES2[9:2]
for non-IP packets (L2T set).
Finally, disable the variable-length preamble when L2 splitting
is enabled. A variable-length preamble shifts the position of the
Ethernet header, making the L2 split offset non-deterministic.
Co-developed-by: Abhishek Chauhan <redacted>
Signed-off-by: Abhishek Chauhan <redacted>
Co-developed-by: Sarosh Hasan <redacted>
Signed-off-by: Sarosh Hasan <redacted>
Signed-off-by: Sagar Cheluvegowda <redacted>
---
v2:
- Add XGMAC_CONFIG1_SPLM_MASK and use it in XGMAC_CONFIG1_SPLM()
v1: https://lore.kernel.org/netdev/20260922232116.889630-1-sagar.cheluvegowda@oss.qualcomm.com/ (local)
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 8 ++++++++
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c | 12 +++++++++++-
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 10 ++++++++++
3 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index f8ab347f7b5b..fb29dd489714 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h@@ -167,6 +167,12 @@ #define XGMAC_HW_FEATURE4 0x0000012c #define XGMAC_HWFEAT_EASP BIT(4) #define XGMAC_HWFEAT_PCSEL GENMASK(1, 0) +#define XGMAC_EXT_CFG0 0x140 +#define XGMAC_EXT_CFG0_VPRE BIT(8) +#define XGMAC_EXT_CFG1 0x00000144 +#define XGMAC_CONFIG1_SAVE_EN BIT(24) +#define XGMAC_CONFIG1_SPLM_MASK GENMASK(9, 8) +#define XGMAC_CONFIG1_SPLM(v) FIELD_PREP(XGMAC_CONFIG1_SPLM_MASK, v) #define XGMAC_MAC_DPP_FSM_INT_STATUS 0x00000150 #define XGMAC_MAC_FSM_CONTROL 0x00000158 #define XGMAC_PRTYEN BIT(1)
@@ -434,6 +440,7 @@ #define XGMAC_RDES2_L4FM BIT(28) #define XGMAC_RDES2_L3FM BIT(27) #define XGMAC_RDES2_HL GENMASK(9, 0) +#define XGMAC_RDES2_NONIPHL GENMASK(9, 2) #define XGMAC_RDES3_OWN BIT(31) #define XGMAC_RDES3_CTXT BIT(30) #define XGMAC_RDES3_IOC BIT(30)
@@ -441,6 +448,7 @@ #define XGMAC_RDES3_CDA BIT(27) #define XGMAC_RDES3_RSV BIT(26) #define XGMAC_RDES3_L34T GENMASK(23, 20) +#define XGMAC_RDES3_L2T GENMASK(19, 16) #define XGMAC_RDES3_ET_LT GENMASK(19, 16) #define XGMAC_L34T_IP4TCP 0x1 #define XGMAC_L34T_IP4UDP 0x2
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
index 6719ac6e395b..65ac5403ec58 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c@@ -292,8 +292,18 @@ static int dwxgmac2_get_rx_hash(struct dma_desc *p, u32 *hash, static void dwxgmac2_get_rx_header_len(struct dma_desc *p, unsigned int *len) { - if (le32_to_cpu(p->des3) & XGMAC_RDES3_L34T) + u32 rdes3 = le32_to_cpu(p->des3); + + /* when FD=1 and LD=0, HL is RDES2[9:0] */ + if (!(rdes3 & XGMAC_RDES3_LD)) { + *len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL; + return; + } + + if (rdes3 & XGMAC_RDES3_L34T) *len = le32_to_cpu(p->des2) & XGMAC_RDES2_HL; + else if (rdes3 & XGMAC_RDES3_L2T) + *len = (le32_to_cpu(p->des2) & XGMAC_RDES2_NONIPHL) >> 2; } static void dwxgmac2_set_sec_addr(struct dma_desc *p, dma_addr_t addr, bool is_valid)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index ff83858ebc1f..0a9c787305a4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c@@ -561,6 +561,16 @@ static void dwxgmac2_enable_sph(struct stmmac_priv *priv, void __iomem *ioaddr, value |= XGMAC_CONFIG_HDSMS_256; /* Segment max 256 bytes */ writel(value, ioaddr + XGMAC_RX_CONFIG); + value = readl(ioaddr + XGMAC_EXT_CFG1); + value |= XGMAC_CONFIG1_SPLM(1); + value |= XGMAC_CONFIG1_SAVE_EN; + writel(value, ioaddr + XGMAC_EXT_CFG1); + + /* Disable variable preambles to keep the L2 split offset deterministic. */ + value = readl(ioaddr + XGMAC_EXT_CFG0); + value &= ~XGMAC_EXT_CFG0_VPRE; + writel(value, ioaddr + XGMAC_EXT_CFG0); + value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); if (en) value |= XGMAC_SPH;
--
2.34.1