[PATCH mlx5-next 2/2] net/mlx5: IFC, Add capability bits for virtual LAG
flat view
WARM1d
REVIEWED: 3 (2M)
From: Tariq Toukan <tariqt@nvidia.com>
Date: 2026-10-05 08:41:32
Also in:
linux-rdma, lkml
Subsystem:
mellanox mlx5 ib driver, mellanox mlx5 core vpi driver, the rest · Maintainers:
Leon Romanovsky, Saeed Mahameed, Tariq Toukan, Mark Bloch, Linus Torvalds
2 review trailers (1 from subsystem maintainers).
From: Shay Drory <redacted> Virtual LAG can also be built over virtual uplinks rather than physical ports. The support for this virtual LAG is indicated by multi_uplink_eswitch and port_select_eswitch caps bit. Signed-off-by: Shay Drory <redacted> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Reviewed-by: Moshe Shemesh <redacted> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> --- include/linux/mlx5/mlx5_ifc.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 989408764e1b..f1ee35aa884a 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h@@ -929,7 +929,7 @@ struct mlx5_ifc_flow_table_nic_cap_bits { struct mlx5_ifc_port_selection_cap_bits { u8 reserved_at_0[0x10]; u8 port_select_flow_table[0x1]; - u8 reserved_at_11[0x1]; + u8 port_select_eswitch[0x1]; u8 port_select_flow_table_bypass[0x1]; u8 reserved_at_13[0xd];
@@ -2010,7 +2010,9 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_3b0[0x2]; u8 qp_latency_sensitive_disable[0x1]; u8 log_max_stride_sz_sq[0x5]; - u8 reserved_at_3b8[0x3]; + u8 reserved_at_3b8[0x1]; + u8 multi_uplink_eswitch[0x1]; + u8 reserved_at_3ba[0x1]; u8 log_min_stride_sz_sq[0x5]; u8 hairpin[0x1];
--
2.44.0