[PATCH net v2 0/2] dpll: zl3073x: fix output pin esync and sibling notifications

This series fixes two issues in the zl3073x output pin handling.

Patch 1 makes the embedded sync (eSync) configuration follow the output
carrier frequency. Changing an output pin's frequency did not update its
eSync period/width, so eSync ran at the wrong rate and, for a 1 Hz
carrier, could get stuck on because esync_get() hides it. This was hit
during development and confirmed on an oscilloscope.

Patch 2 notifies the sibling pin of an output pair when a shared HW
setting (divisor, clock type, eSync period/width, phase compensation) is
changed through one pin, so userspace is told the change happened.

Changes since v1:
- Patch 1: pass the actual output carrier (synth_freq / out.div) to
  zl3073x_out_esync_enable() in the frequency change path, matching
  esync_set(), instead of the raw requested frequency (no functional
  change, output frequencies always divide the synth frequency); drop
  the redundant "? true : false" in zl3073x_out_esync_is_enabled()
  reported by coccinelle (boolconv); fix a comment typo.
- No other functional changes; both commit messages now describe how the
  issues were found and whether they were triggered, as requested on the
  v1 thread.

v1: https://lore.kernel.org/netdev/20261001080648.1424172-1-ivecera@redhat.com/ (local)

Ivan Vecera (2):
  dpll: zl3073x: make embedded sync follow the output carrier frequency
  dpll: zl3073x: notify sibling pin when shared output config changes

 drivers/dpll/zl3073x/dpll.c | 196 ++++++++++++++++++++++++++----------
 drivers/dpll/zl3073x/out.h  |  34 +++++++
 2 files changed, 176 insertions(+), 54 deletions(-)

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2.55.0