Re: [PATCH RFC v3 04/12] net: pcs: add NXP SerDes XPCS shared core

On Sat, Sep 19, 2026 at 08:54:32AM +0200, Jan Petrous via B4 Relay wrote:

From: Clark Wang <xiaoning.wang@nxp.com>

The SerDes subsystems found on NXP S32G and i.MX SoCs integrate a
Synopsys DesignWare Ethernet XPCS and an Ethernet PHY (PMA) with an
identical register layout. Only the register transport differs: indirect
memory mapped access on S32G, Clause 45 MDIO on i.MX.

Add a transport agnostic phylink PCS core which operates on regmaps
provided by the platform glue.

What is not transport agnostic with the current code.

Think carefully about that, before you answer.

	Andrew