[PATCH iwl-net 0/2] ice: DPLL init fixes for E810 timing boards

Two fixes for E810-C timing boards the driver's static pin tables were
not written for, seen on a board whose netlist has no PCA9575 clock mux
and whose CGU reports more pins than the tables describe. The first
layout is a reference design of its own, Intel ships it as the
E810_C827_SyncE_SFP_SEC NVM configuration.

Patch 1 keeps the DPLL registration alive when the PCA9575 clock mux is
missing. Today the lookup fails and the driver gives up on the whole
DPLL, so userspace loses both devices and every pin.

Patch 2 stops the SMA and U.FL wrapper setup from indexing the input
and output arrays at fixed positions when the driver has already fallen
back to generic pins, where those positions can lie past the end of the
arrays.

Both are tested on an E810-T with the mux present, with the mux hidden
from the driver, and with the generic pin path forced, and on the board
above, where both DPLLs now lock.

A follow-up for iwl-next derives the generic pin names from the pin
classification the firmware reports, so such boards get addressable
pins instead of ambiguous numbers.

Petr Oros (2):
  ice: fix DPLL registration on boards without the SMA clock mux
  ice: skip the SW pin description on boards with generic DPLL pins

 drivers/net/ethernet/intel/ice/ice_dpll.c | 33 +++++++++++++++++------
 1 file changed, 25 insertions(+), 8 deletions(-)

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2.55.0