[PATCH v5 5/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R5S
From: Ricardo Pardini via B4 Relay <devnull+ricardo.pardini.net@kernel.org>
Date: 2026-09-10 20:08:06
Also in:
b4-sent, linux-arm-kernel, linux-devicetree, linux-rockchip, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
From: Ricardo Pardini <redacted> The FriendlyElec NanoPi R5S (rk3568) carries two on-board Realtek RTL8125 NICs behind pcie2x1 and pcie3x1, alongside the existing gmac0 RGMII PHY. Describe the fixed function nodes and attach ethernet1/ethernet2 aliases (ethernet0 stays mapped to gmac0), so that U-Boot's fdt_fixup_ethernet() can inject mac-address properties from its eth1addr/eth2addr env, for stable MACs across boots that both U-Boot and the kernel agree on. Signed-off-by: Ricardo Pardini <redacted> --- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
index 90ce6f0e1dcff..9ed11663c31c9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts@@ -15,6 +15,8 @@ / { aliases { ethernet0 = &gmac0; + ethernet1 = &rtl_eth1; + ethernet2 = &rtl_eth2; }; gpio-keys {
@@ -107,6 +109,20 @@ &pcie2x1 { num-lanes = <1>; reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; status = "okay"; + + pcie@0,0 { + reg = <0x000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x00 0x0f>; + + rtl_eth1: ethernet@0,0 { + compatible = "pci10ec,8125"; + reg = <0x010000 0 0 0 0>; + }; + }; }; &pcie30phy {
@@ -119,6 +135,20 @@ &pcie3x1 { reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; + + pcie@0,0 { + reg = <0x100000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x10 0x1f>; + + rtl_eth2: ethernet@0,0 { + compatible = "pci10ec,8125"; + reg = <0x110000 0 0 0 0>; + }; + }; }; &pcie3x2 {
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2.55.0