[PATCH PRELIMINARY 2/5] arm64: dts: qcom: shikra: add ethernet nodes
From: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Date: 2026-09-08 06:23:56
Also in:
linux-arm-msm, linux-devicetree, lkml
Subsystem:
arm/qualcomm mailing list, arm/qualcomm support, the rest · Maintainers:
Bjorn Andersson, Konrad Dybcio, Linus Torvalds
Add the two Gigabit Ethernet controllers present on Shikra (ethernet0 at 0x5d00000, ethernet1 at 0x5d20000). Both nodes are left disabled; board files supply the PHY details. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/shikra.dtsi | 266 +++++++++++++++++++++++++++++++++++ 1 file changed, 266 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index c1f06f692f66452c6ee1b10f3ef12c20e201b5ce..a55e20be83fe2d132eb91878e76b666b8694da55 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi@@ -631,6 +631,56 @@ tlmm: pinctrl@500000 { gpio-ranges = <&tlmm 0 0 165>; wakeup-parent = <&mpm>; + ethernet0_default: ethernet0-default-state { + rgmii-rx-pins { + pins = "gpio121", "gpio122", "gpio123", + "gpio124", "gpio125", "gpio126"; + function = "rgmii"; + drive-strength = <16>; + bias-disable; + }; + + rgmii-tx-pins { + pins = "gpio127", "gpio128", "gpio129", + "gpio130", "gpio131", "gpio132"; + function = "rgmii"; + drive-strength = <16>; + bias-pull-up; + }; + + rgmii-mdio-pins { + pins = "gpio133", "gpio134"; + function = "rgmii"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ethernet1_default: ethernet1-default-state { + rgmii-rx-pins { + pins = "gpio137", "gpio138", "gpio139", + "gpio140", "gpio141", "gpio142"; + function = "rgmii"; + drive-strength = <16>; + bias-disable; + }; + + rgmii-tx-pins { + pins = "gpio143", "gpio144", "gpio145", + "gpio146", "gpio147", "gpio148"; + function = "rgmii"; + drive-strength = <16>; + bias-pull-up; + }; + + rgmii-mdio-pins { + pins = "gpio149", "gpio150"; + function = "rgmii"; + drive-strength = <16>; + bias-pull-up; + }; + }; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { /* SDA, SCL */ pins = "gpio2", "gpio3";
@@ -1977,6 +2027,222 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, }; }; + ethernet0: ethernet@5d00000 { + compatible = "qcom,shikra-ethqos"; + reg = <0x0 0x05d00000 0x0 0x10000>, + <0x0 0x05d16000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq"; + + clocks = <&gcc GCC_EMAC0_AXI_CLK>, + <&gcc GCC_EMAC0_AHB_CLK>, + <&gcc GCC_EMAC0_PTP_CLK>, + <&gcc GCC_EMAC0_RGMII_CLK>, + <&gcc GCC_EMAC0_AXI_SYS_NOC_CLK>, + <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii", + "axi-noc", "pcie-tile-axi-noc"; + + power-domains = <&gcc GCC_EMAC0_GDSC>; + resets = <&gcc GCC_EMAC0_BCR>; + iommus = <&apps_smmu 0x0380 0x0007>; + + interconnects = <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_EMAC0_CFG QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_EMAC_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-mac", "mac-mem"; + + operating-points-v2 = <&emac0_opp_table>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <16384>; + + snps,mtl-rx-config = <&emac0_mtl_rx_setup>; + snps,mtl-tx-config = <&emac0_mtl_tx_setup>; + + status = "disabled"; + + emac0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmpd_opp_svs>; + }; + }; + + emac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + emac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; + }; + + ethernet1: ethernet@5d20000 { + compatible = "qcom,shikra-ethqos"; + reg = <0x0 0x05d20000 0x0 0x10000>, + <0x0 0x05d36000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq"; + + clocks = <&gcc GCC_EMAC1_AXI_CLK>, + <&gcc GCC_EMAC1_AHB_CLK>, + <&gcc GCC_EMAC1_PTP_CLK>, + <&gcc GCC_EMAC1_RGMII_CLK>, + <&gcc GCC_EMAC1_AXI_SYS_NOC_CLK>, + <&gcc GCC_PCIE_TILE_AXI_SYS_NOC_CLK>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii", + "axi-noc", "pcie-tile-axi-noc"; + + power-domains = <&gcc GCC_EMAC1_GDSC>; + resets = <&gcc GCC_EMAC1_BCR>; + iommus = <&apps_smmu 0x03a0 0x0007>; + + interconnects = <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>, + <&system_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-mac", "mac-mem"; + + operating-points-v2 = <&emac1_opp_table>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <16384>; + + snps,mtl-rx-config = <&emac1_mtl_rx_setup>; + snps,mtl-tx-config = <&emac1_mtl_tx_setup>; + + status = "disabled"; + + emac1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + required-opps = <&rpmpd_opp_svs>; + }; + }; + + emac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + emac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; + }; + remoteproc_mpss: remoteproc@6080000 { compatible = "qcom,shikra-mpss-pas"; reg = <0x0 0x06080000 0x0 0x100>;
--
2.34.1