[PATCH iwl-next v3 1/6] ice: dpll: Add the MUX tables to the documentation
From: Sergey Temerkhanov <hidden>
Date: 2026-08-21 15:25:02
Also in:
intel-wired-lan
Subsystem:
intel ethernet drivers, networking drivers, the rest · Maintainers:
Tony Nguyen, Przemek Kitszel, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
Add the tables documenting the DPLL pin MUX states and behavior to the driver. Signed-off-by: Sergey Temerkhanov <redacted> --- drivers/net/ethernet/intel/ice/ice_dpll.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
index 382fbe98f2b0..9b3584fa43a9 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c@@ -92,6 +92,29 @@ static const struct dpll_pin_frequency ice_esync_range[] = { DPLL_PIN_FREQUENCY_RANGE(0, DPLL_PIN_FREQUENCY_1_HZ), }; +/* + * SMA1/U.FL1 MUX table + *+----------------+-------------+------------+ + *| | SMA1_DIR_EN | SMA1_TX_EN | + *+----------------+-------------+------------+ + *|SMA1 RX Enable | 0 | x | + *|u.FL1 TX Enable | 0 | 0 | + *|SMA1 TX Enable | 1 | 0 | + *|All Disable | 1 | 1 | + *+----------------+-------------+------------+ + * + * SMA2/U.FL2 MUX table + *+----------------+-------------+------------+------------+ + *| | SMA2_DIR_EN | SMA2_TX_EN | UFL2_RX_EN | + *+----------------+-------------+------------+------------+ + *|SMA2 RX Enable | 0 | x | x | + *|u.FL2 RX Enable | 1 | x | 0 | + *|SMA2 TX Enable | 1 | 0 | x | + *|SMA2 Disable | 1 | 1 | x | + *|All Disable | 1 | 1 | 1 | + *+----------------+-------------+------------+------------+ + */ + /** * ice_dpll_is_sw_pin - check if given pin shall be controlled by SW * @pf: private board structure
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2.53.0