Re: [PATCH v6] net: airoha: npu: use coherent DMA for mailbox messages

On Sun,  9 Aug 2026 17:28:13 +0200 Daniel Pawlik wrote:

Commit 6f884eb87a79 ("net: airoha: Fix DMA direction for NPU mailbox
buffer") switched airoha_npu_send_msg() to DMA_BIDIRECTIONAL so
non-coherent CPUs invalidate caches before reading NPU GET responses.

On EN7581 + MT7996 that change regresses probe: the mailbox completes
successfully, but WLAN_FUNC_GET_WAIT_NPU_VERSION still reads as 0.0 and
mt76 never binds NPU offload. Healthy boards report 0.1111.

This sounds very odd. Is the DMA API broken on the platforms you are
testing? The code looks correct as is.

FWIW here's what GPT suggests:

  Indeed, HEAD^ uses the DMA API correctly:
  DMA_BIDIRECTIONAL map/unmap must make the NPU response visible to the CPU.

  The important wrinkle is that, on arm64, these small kzalloc() buffers are
  forced through SWIOTLB when mapped bidirectionally. DMA_TO_DEVICE did not
  bounce them. HEAD switches to coherent memory and therefore bypasses SWIOTLB
  entirely. That suggests the actual problem is one of:

  - SWIOTLB memory is outside the NPU’s real DMA aperture.
  - The platform’s dma-ranges/DMA mask does not describe that aperture.
  - SWIOTLB copyback or cache handling is broken.

  Using coherent memory for a mailbox is reasonable, but this patch masks that
  underlying problem rather than explaining it. Before accepting it, I would
  test a cacheline-aligned, rounded-size streaming buffer with
  DMA_BIDIRECTIONAL, while programming the original payload length into the
  mailbox. If that works, it strongly implicates the SWIOTLB/platform setup.

We can take a revert of the patch under Fixes if it's urgent.
The real fix requires a deeper investigation.
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