Re: [PATCH v9] ptp: ocp: add CPLD ISP support for ADVA TimeCard X1

On 03/08/2026 15:28, Sagi Maimon wrote:

The ADVA TimeCard X1 (PCI device 0x0410) uses a Lattice MachXO3 CPLD
that is programmed over I2C using in-system programming (ISP).

The CPLD is connected to a secondary I2C bus shared with the onboard
MicroBlaze soft CPU.

Add support for CPLD access and firmware updates on the ADVA TimeCard X1
board by arbitration of the shared I2C bus, CPLD ISP command handling,
status polling, and firmware upload operations using the firmware-upload
subsystem.

Add the following X1-only user-visible interfaces:

   /sys/class/timecard/ocpN/cpld_device_id
         report the 32-bit Lattice MachXO3 CPLD device ID

   /sys/class/timecard/ocpN/cpld_status
         report the CPLD status register, including the DONE,
         BUSY, and FAILED indicators

Firmware updates are performed through the firmware-upload framework,
which acquires ownership of the shared I2C bus, erases the CPLD
configuration flash, programs the image page-by-page, and activates
the new image using the MachXO3 REFRESH command.

All CPLD operations are serialized and coordinated with the MicroBlaze
firmware to ensure exclusive access to the shared I2C bus. The added
interfaces are available only on ADVA TimeCard X1 boards.

Signed-off-by: Sagi Maimon <redacted>
---
  
  Changes since v8:
  - Use dedicated MicroBlaze handshake values instead of 0xffffffff,
    which may be returned by failed PCI reads.

Please, combine it with comments on v8

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pw-bot: cr