[PATCH net-next v3 0/3] dpll: zl3073x: add PTP clock support

Add PTP hardware clock support to the zl3073x DPLL driver.

Patch 1 adds low-level channel operations for ToD read/write/adjust,
output phase step, delta frequency offset write and TIE write as
building blocks for PTP callbacks.

Patch 2 factors out the output pin frequency setting logic into an
unlocked helper callable from internal contexts.

Patch 3 registers a PTP clock device for each DPLL channel with
gettimex64, settime64, adjtime, adjfine, adjphase, getmaxphase
and perout callbacks. Callback availability adapts to the current
channel state - adjfine requires NCO pin connected, adjphase uses
TIE write when tracking a reference, and adjtime selects the
appropriate mechanism automatically.

Link: https://lore.kernel.org/netdev/20260713103739.1553284-1-ivecera@redhat.com/ (local)
Link: https://lore.kernel.org/netdev/20260708170527.916035-1-ivecera@redhat.com/ (local)

Changes:
v3:
  - Use PTP_1588_CLOCK instead of PTP_1588_CLOCK_OPTIONAL (Jakub)
  - Factor out output pin frequency helper to a separate commit (Jakub)
  - Remove spurious #include <linux/mutex.h> from dpll.h (Jakub)
v2:
  - Squash low-level ops patches (1+3) into patch 1.
  - Squash PTP callback patches (2+4) into patch 2, register PTP
    clock regardless of initial channel state.

Ivan Vecera (3):
  dpll: zl3073x: add channel ToD, phase step and TIE operations
  dpll: zl3073x: refactor output pin frequency set for internal use
  dpll: zl3073x: add PTP clock support

 drivers/dpll/zl3073x/Kconfig |   6 +-
 drivers/dpll/zl3073x/chan.c  | 307 +++++++++++++++++++
 drivers/dpll/zl3073x/chan.h  |  48 +++
 drivers/dpll/zl3073x/core.c  |   8 +
 drivers/dpll/zl3073x/core.h  |   8 +
 drivers/dpll/zl3073x/dpll.c  | 575 +++++++++++++++++++++++++++++++++--
 drivers/dpll/zl3073x/dpll.h  |   5 +
 drivers/dpll/zl3073x/regs.h  |  56 ++++
 8 files changed, 977 insertions(+), 36 deletions(-)


base-commit: a5c6ae8de11ef0c3aedbe5e123354aad87d0d925
-- 
2.54.0