[PATCH net-next v3] net: phy: motorcomm: enable the reference clock for YT8521 and YT8531
From: Jiaxing Hu <hidden>
Date: 2026-07-28 04:57:39
Also in:
linux-rockchip, lkml
Subsystem:
ethernet phy library, motorcomm phy driver, networking drivers, the rest · Maintainers:
Andrew Lunn, Heiner Kallweit, Frank, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
These PHYs need a 25 MHz reference. On boards without a local crystal it is fed from the SoC and described as a clock on the PHY node. Get and enable it in probe, in both yt8521_probe and yt8531_probe, so the PHY is clocked before its registers are accessed. The clock is optional, so crystal-clocked boards are unaffected. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Gavin Gao <redacted> Signed-off-by: Jiaxing Hu <redacted> --- Changes in v3: - Open-code the clock enable in yt8521_probe and yt8531_probe instead of a helper; the block is short and self-explanatory inline (Alexey Charkov). No functional change, so Andrew's Reviewed-by and Gavin's Tested-by are carried over. Changes in v2: - Also enable the reference clock for the YT8521, not only the YT8531. v1: https://lore.kernel.org/all/20260719034555.3623003-1-gahing@gahingwoo.com/ (local) v2: https://lore.kernel.org/all/20260727205602.1188008-1-gahing@gahingwoo.com/ (local) The DTS that consumes the clock (rk3576-armsom-cm5) goes to the rockchip tree separately; the clock is optional so this patch stands alone. Tested on an ArmSoM CM5-IO (YT8531) and a PicoCOM RK3576 board (YT8521). drivers/net/phy/motorcomm.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index 708491bc1..bb2e9f4f5 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c@@ -6,6 +6,7 @@ * Author: Frank <Frank.Sae@motor-comm.com> */ +#include <linux/clk.h> #include <linux/etherdevice.h> #include <linux/kernel.h> #include <linux/module.h>
@@ -1053,6 +1054,7 @@ static int yt8521_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; struct yt8521_priv *priv; + struct clk *clk; int chip_config; u16 mask, val; u32 freq;
@@ -1064,6 +1066,12 @@ static int yt8521_probe(struct phy_device *phydev) phydev->priv = priv; + /* A crystal-less PHY is fed its 25 MHz reference from the SoC. */ + clk = devm_clk_get_optional_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "failed to get and enable the reference clock\n"); + chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); if (chip_config < 0) return chip_config;
@@ -1169,9 +1177,16 @@ static int yt8521_probe(struct phy_device *phydev) static int yt8531_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; + struct clk *clk; u16 mask, val; u32 freq; + /* A crystal-less PHY is fed its 25 MHz reference from the SoC. */ + clk = devm_clk_get_optional_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "failed to get and enable the reference clock\n"); + if (device_property_read_u32(dev, "motorcomm,clk-out-frequency-hz", &freq)) freq = YTPHY_DTS_OUTPUT_CLK_DIS;
--
2.43.0