[PATCH net-next v2] net: phy: motorcomm: enable the reference clock for YT8521 and YT8531
From: Jiaxing Hu <hidden>
Date: 2026-07-27 21:05:07
Also in:
linux-rockchip, lkml
Subsystem:
ethernet phy library, motorcomm phy driver, networking drivers, the rest · Maintainers:
Andrew Lunn, Heiner Kallweit, Frank, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
These PHYs need a 25 MHz reference. On boards without a local crystal it is fed from the SoC and described as a clock on the PHY node. Get and enable it in probe, via a small helper called from both yt8521_probe and yt8531_probe, so the PHY is clocked before its registers are accessed. The clock is optional, so crystal-clocked boards are unaffected. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jiaxing Hu <redacted> --- Changes in v2: - Factor the clock enable into ytphy_get_and_enable_refclk() and call it from yt8521_probe as well, so the YT8521 is covered too, not only the YT8531. v1 only touched yt8531_probe. - Carried Andrew's Reviewed-by; the enable itself is unchanged, only moved into the helper. v1: https://lore.kernel.org/all/20260719034555.3623003-1-gahing@gahingwoo.com/ (local) A second crystal-less RK3576 board with a YT8521 needs the same handling (see the RK3576 GMAC 25M refout thread [1]), so v2 covers both PHYs. This supersedes the withdrawn dwmac-rk MAC-side series. The DTS that consumes the clock (rk3576-armsom-cm5) goes to the rockchip tree separately; the clock is optional so this patch stands alone. The YT8531 path is tested on an ArmSoM CM5-IO (links at 1000 Mbit/s). [1] https://lore.kernel.org/all/20260727021048.3375444-1-attinagaoxu@gmail.com/ (local) drivers/net/phy/motorcomm.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index 708491bc1..32eb5ce93 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c@@ -6,6 +6,7 @@ * Author: Frank <Frank.Sae@motor-comm.com> */ +#include <linux/clk.h> #include <linux/etherdevice.h> #include <linux/kernel.h> #include <linux/module.h>
@@ -1043,6 +1044,29 @@ static int yt8531_set_ds(struct phy_device *phydev) return 0; } +/** + * ytphy_get_and_enable_refclk() - get and enable the PHY reference clock + * @phydev: a pointer to a &struct phy_device + * + * A crystal-less YT8521/YT8531 takes its 25 MHz reference from the SoC. When + * that reference is described as a clock, enable it for the life of the + * device. It is optional, so crystal-clocked boards are unaffected. + * + * returns 0 or negative errno code + */ +static int ytphy_get_and_enable_refclk(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct clk *clk; + + clk = devm_clk_get_optional_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "failed to get and enable the reference clock\n"); + + return 0; +} + /** * yt8521_probe() - read chip config then set suitable polling_mode * @phydev: a pointer to a &struct phy_device
@@ -1064,6 +1088,10 @@ static int yt8521_probe(struct phy_device *phydev) phydev->priv = priv; + ret = ytphy_get_and_enable_refclk(phydev); + if (ret) + return ret; + chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); if (chip_config < 0) return chip_config;
@@ -1171,6 +1199,11 @@ static int yt8531_probe(struct phy_device *phydev) struct device *dev = &phydev->mdio.dev; u16 mask, val; u32 freq; + int ret; + + ret = ytphy_get_and_enable_refclk(phydev); + if (ret) + return ret; if (device_property_read_u32(dev, "motorcomm,clk-out-frequency-hz", &freq)) freq = YTPHY_DTS_OUTPUT_CLK_DIS;
--
2.43.0