This series reworks and clarifies ice DPLL control logic.
Contains refactoring changes for better readability and
maintainability as well as the changes making the pin
controls compliant to design requirements.
v1->v2: Harden the error handling paths, additional bounds and
pointer checks
Sergey Temerkhanov (4):
ice: dpll: Rework multiplexed pin notifications
ice: dpll: Use switch statements to handle pin states
ice: dpll: Rework U.FL muxed pin (SMA) control
ice: dpll: Rework the SMA control logic to match the requirements
drivers/net/ethernet/intel/ice/ice_dpll.c | 347 ++++++++++++++++++----
drivers/net/ethernet/intel/ice/ice_dpll.h | 1 +
2 files changed, 290 insertions(+), 58 deletions(-)
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2.53.0