Re: [PATCH net-next v5] net: phy: Add driver for Motorcomm Quad 2.5GbE phy

On 7/21/26 21:27, Andrew Lunn wrote:

quoted

+#define YT8824_UTP_TEMPLATE_MODE_CTRL		(0x84)
+#define YT8824_UTP_TEMPLATE_MODE_MASK		GENMASK(15, 13)
+#define YT8824_UTP_TEMPLATE_TEST_MODE1		BIT(13)

Is this MultiGBASE-T test mode register (Register 1.132)?

The test mode control is not a single bit, but three bits. So you
should not be using BIT(13).

Since this is a standard part of C45, please add a helper to phy-c45.c

Another thing i want to take a look at is the locking. It is pretty
ugly having to use so many __ functions, and not being able to use the
helpers. I want to see if we can avoid this.

    Andrew

Ans: yes, it is standard MultiGBASE-T test mode register.

     I will add a helper similar to genphy_c45_template_test_mode() in
     phy-c45.c in patch v6.
     
     I have a question and would appreciate your advice.As previously discussed,
     for phy8824, the page select register is in top extend reg space shared by
     four PHYS in one phy-package. Within a functional ops in phy8824 driver, 
     it is necessary to take a bus lock at the beginning and unlock the bus 
     at the end of the function, that is why many __functions are needed.For the 
     same issue, when calling genphy_c45_template_test_mode() within phy8824 ops, 
     it is also necessary to ensure that the operation within 
     genphy_c45_template_test_mode() is a __function, which is inconsistent with 
     other interfaces in phy-c45.c.
     Could you give me some suggestions on this issue?

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pw-bot: cr