[PATCH iwl-next v1 2/4] ice: dpll: Use switch statements to handle pin states
From: Sergey Temerkhanov <hidden>
Date: 2026-07-16 09:49:19
Also in:
intel-wired-lan
Subsystem:
intel ethernet drivers, networking drivers, the rest · Maintainers:
Tony Nguyen, Przemek Kitszel, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
Use switch statements to handle pin states to make the code more readable. This also makes this code more future-proof, should any new states appear. This also changes how direction-mismatched state requests are handled in ice_dpll_sma_pin_state_set(). Previously, requesting CONNECTED on an INPUT-direction SMA pin or SELECTABLE on an OUTPUT-direction pin would fall through to ice_dpll_pin_disable() and return success. After this change those requests return -EINVAL without issuing a firmware command. Because the DPLL netlink core does not filter pin states by direction before calling the driver, this is a user-visible netlink API change. Signed-off-by: Sergey Temerkhanov <redacted> Reviewed-by: Aleksandr Loktionov <redacted> Reviewed-by: Przemyslaw Korba <redacted> --- drivers/net/ethernet/intel/ice/ice_dpll.c | 65 ++++++++++++++++++----- 1 file changed, 53 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
index fed7c9fea953..54958e17713b 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c@@ -1320,10 +1320,12 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, ret = -EINVAL; switch (p->idx) { case ICE_DPLL_PIN_SW_1_IDX: - if (state == DPLL_PIN_STATE_CONNECTED) { + switch (state) { + case DPLL_PIN_STATE_CONNECTED: data &= ~ICE_SMA1_MASK; enable = true; - } else if (state == DPLL_PIN_STATE_DISCONNECTED) { + break; + case DPLL_PIN_STATE_DISCONNECTED: /* Skip if U.FL1 is not active, setting TX_EN * while DIR_EN is set would also deactivate * the paired SMA1 output.
@@ -1334,18 +1336,21 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, } data |= ICE_SMA1_TX_EN; enable = false; - } else { + break; + default: goto unlock; } target = p->output; type = ICE_DPLL_PIN_TYPE_OUTPUT; break; case ICE_DPLL_PIN_SW_2_IDX: - if (state == DPLL_PIN_STATE_SELECTABLE) { + switch (state) { + case DPLL_PIN_STATE_SELECTABLE: data |= ICE_SMA2_DIR_EN; data &= ~ICE_SMA2_UFL2_RX_DIS; enable = true; - } else if (state == DPLL_PIN_STATE_DISCONNECTED) { + break; + case DPLL_PIN_STATE_DISCONNECTED: /* Skip if U.FL2 is not active, setting * UFL2_RX_DIS could also disable the paired * SMA2 input.
@@ -1357,7 +1362,8 @@ ice_dpll_ufl_pin_state_set(const struct dpll_pin *pin, void *pin_priv, } data |= ICE_SMA2_UFL2_RX_DIS; enable = false; - } else { + break; + default: goto unlock; } target = p->input;
@@ -1484,14 +1490,43 @@ ice_dpll_sma_pin_state_set(const struct dpll_pin *pin, void *pin_priv, if (ret) goto unlock; } - if (sma->direction == DPLL_PIN_DIRECTION_INPUT) { - enable = state == DPLL_PIN_STATE_SELECTABLE; + switch (state) { + case DPLL_PIN_STATE_SELECTABLE: + if (sma->direction == DPLL_PIN_DIRECTION_OUTPUT) { + enable = false; + ret = -EINVAL; + goto unlock; + } + enable = true; + break; + case DPLL_PIN_STATE_CONNECTED: + if (sma->direction == DPLL_PIN_DIRECTION_INPUT) { + enable = false; + ret = -EINVAL; + goto unlock; + } + enable = true; + break; + case DPLL_PIN_STATE_DISCONNECTED: + enable = false; + break; + default: + ret = -EINVAL; + goto unlock; + } + + switch (sma->direction) { + case DPLL_PIN_DIRECTION_INPUT: target = sma->input; type = ICE_DPLL_PIN_TYPE_INPUT; - } else { - enable = state == DPLL_PIN_STATE_CONNECTED; + break; + case DPLL_PIN_DIRECTION_OUTPUT: target = sma->output; type = ICE_DPLL_PIN_TYPE_OUTPUT; + break; + default: + ret = -EINVAL; + goto unlock; } if (enable)
@@ -4631,7 +4666,8 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) pin->prop.capabilities = caps; pin->pf = pf; pin->prop.board_label = ice_dpll_sw_pin_ufl[i]; - if (i == ICE_DPLL_PIN_SW_1_IDX) { + switch (i) { + case ICE_DPLL_PIN_SW_1_IDX: pin->direction = DPLL_PIN_DIRECTION_OUTPUT; pin_abs_idx = ICE_DPLL_PIN_SW_OUTPUT_ABS(i); pin->prop.freq_supported =
@@ -4641,7 +4677,8 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) pin->prop.freq_supported_num = freq_supp_num; pin->input = NULL; pin->output = &d->outputs[pin_abs_idx]; - } else if (i == ICE_DPLL_PIN_SW_2_IDX) { + break; + case ICE_DPLL_PIN_SW_2_IDX: pin->direction = DPLL_PIN_DIRECTION_INPUT; pin_abs_idx = ICE_DPLL_PIN_SW_INPUT_ABS(i) + input_idx_offset;
@@ -4654,6 +4691,10 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf) pin->prop.capabilities = (DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE | caps); + break; + default: + dev_err(ice_pf_to_dev(pf), "Invalid U.FL pin index: %d\n", i); + return -EINVAL; } pin->muxed = &d->sma[i]; ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max);
--
2.53.0