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diff --git a/drivers/net/ethernet/freescale/enetc/enetc4_pf.c

b/drivers/net/ethernet/freescale/enetc/enetc4_pf.c

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index cab79f81d6fe0..fcfbabb29d22e 100644

--- a/drivers/net/ethernet/freescale/enetc/enetc4_pf.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc4_pf.c

[ ... ]

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@@ -255,34 +254,35 @@ static void enetc4_default_rings_allocation(struct

enetc_pf *pf)

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 {
 	struct enetc_hw *hw = &pf->si->hw;
 	u32 num_rx_bdr, num_tx_bdr, val;
+	int num_vfs = pf->total_vfs;
 	u32 vf_tx_bdr, vf_rx_bdr;
 	int i, rx_rem, tx_rem;

-	if (pf->caps.num_rx_bdr < ENETC_SI_MAX_RING_NUM +

pf->caps.num_vsi)

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-		num_rx_bdr = pf->caps.num_rx_bdr - pf->caps.num_vsi;
+	if (pf->caps.num_rx_bdr < ENETC_SI_MAX_RING_NUM + num_vfs)
+		num_rx_bdr = pf->caps.num_rx_bdr - num_vfs;
 	else
 		num_rx_bdr = ENETC_SI_MAX_RING_NUM;

-	if (pf->caps.num_tx_bdr < ENETC_SI_MAX_RING_NUM +

pf->caps.num_vsi)

quoted

-		num_tx_bdr = pf->caps.num_tx_bdr - pf->caps.num_vsi;
+	if (pf->caps.num_tx_bdr < ENETC_SI_MAX_RING_NUM + num_vfs)
+		num_tx_bdr = pf->caps.num_tx_bdr - num_vfs;
 	else
 		num_tx_bdr = ENETC_SI_MAX_RING_NUM;

 	val = enetc4_psicfgr0_val_construct(false, num_tx_bdr, num_rx_bdr);
 	enetc_port_wr(hw, ENETC4_PSICFGR0(0), val);

-	if (!pf->caps.num_vsi)
+	if (!num_vfs)
 		return;

[Severity: High]
In enetc4_default_rings_allocation(), when num_vfs is 0 (such as when
CONFIG_PCI_IOV is disabled), this returns early without zeroing the ring
allocations in the VSIs' PSICFGR0 registers.

Because num_vfs is 0 instead of the true physical VSI count, the PF is
allocated the maximum possible hardware rings.

If these VSI registers retain non-zero values (e.g., from firmware defaults
or after a warm reboot), won't the sum of configured rings across the PF and
VSIs strictly exceed the physical hardware capacity?

Could this lead to memory corruption within the ENETC device's internal
SRAM or cause DMA issues due to overlapping BD ring structures?

The PF performs PCIe FLR when the driver probes, it will reset all the registers.
The default values of VSIs' PSICFGR0 registers are 0.