[PATCH v2 3/5] net: phy: motorcomm: Enable optional clock for YT8531
From: Yanan He <hidden>
Date: 2026-07-06 09:15:41
Also in:
linux-arm-kernel, linux-devicetree, linux-rockchip, lkml
Subsystem:
ethernet phy library, motorcomm phy driver, networking drivers, the rest · Maintainers:
Andrew Lunn, Heiner Kallweit, Frank, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
Some boards feed the YT8531 PHY from an SoC-provided external reference clock described by the common ethernet-phy "clocks" property. Enable the optional PHY clock during probe so boards can model this clock as a PHY input instead of keeping the clock alive from the MAC driver. This is needed on the Alientek DLRV1126, where the PHY reference clock is provided by CLK_GMAC_ETHERNET_OUT. Signed-off-by: Yanan He <redacted> --- drivers/net/phy/motorcomm.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
index 5071605a1a11..3396a38cfc0f 100644
--- a/drivers/net/phy/motorcomm.c
+++ b/drivers/net/phy/motorcomm.c@@ -6,6 +6,7 @@ * Author: Frank <Frank.Sae@motor-comm.com> */ +#include <linux/clk.h> #include <linux/etherdevice.h> #include <linux/kernel.h> #include <linux/module.h>
@@ -1180,9 +1181,15 @@ static int yt8521_probe(struct phy_device *phydev) static int yt8531_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; + struct clk *clk; u16 mask, val; u32 freq; + clk = devm_clk_get_optional_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "failed to get and enable PHY clock\n"); + if (device_property_read_u32(dev, "motorcomm,clk-out-frequency-hz", &freq)) freq = YTPHY_DTS_OUTPUT_CLK_DIS;
--
2.54.0