Re: [PATCH v3 1/1] bus: mhi: pci_generic: fix Rolling Wireless RW135R-GL and RW151 support
From: Krishna Chaitanya Chundru <hidden>
Date: 2026-07-02 04:31:29
Also in:
linux-arm-msm
On 7/1/2026 3:23 PM, zwq2226404116@163.com wrote:
From: Wanquan Zhong <redacted> bus: mhi: pci_generic: fix Rolling Wireless RW135R-GL and RW151 support - Increase RW151 MBIM channel ring size from 4 to 32 On HP and Lenovo laptop platforms the device probes successfully and WWAN ports are created, but pci_generic enables runtime autosuspend (PCI D3hot/M3) after a short idle period. Resume from runtime PM leaves the modem in MHI SYS ERROR; driver recovery (reset) fails and the device becomes inaccessible (PCIe config space reads as 0x7f). The failure is not self-recoverable while runtime PM remains enabled; keeping power/control=on avoids the issue.
This might not be MHI issue, as the endpoint supports both D3hot and M3. After runtime suspend check what does your platform is doing as part of runtime suspend. It is more like a platform issue not a mhi issue. The change is like workaround on platform problem. so for the change no_m3 = true is not correct. - Krishna Chaitanya.
quoted hunk ↗ jump to hunk
Set no_m3 on RW135R-GL and RW151 so probe does not enable runtime M3 autosuspend for these modules. Power management testing (separate from runtime PM above): - Suspend-to-RAM (S3/mem): tested on RW135R-GL and RW151; MHI/MBIM/wwan function after wake. - Suspend-to-disk (hibernate): not available on the test platforms (/sys/power/state lacks "disk", ENODEV). Signed-off-by: Wanquan Zhong <redacted> --- v2 -> v3: RW151 MBIM ring size 32; disable runtime M3 (no_m3) drivers/bus/mhi/host/pci_generic.c | 4 +++- 1 file changed, 4 insertions(+), 2 deletions(-)diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c index d598bb3b3981..d0fee7e3ba3a 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c@@ -942,6 +942,7 @@ static const struct mhi_pci_dev_info mhi_rolling_rw135r_info = { .bar_num = MHI_PCI_DEFAULT_BAR_NUM, .dma_data_width = 32, .sideband_wake = false, + .no_m3 = true, .mru_default = 32768, .edl_trigger = true, };@@ -949,8 +950,8 @@ static const struct mhi_pci_dev_info mhi_rolling_rw135r_info = { static const struct mhi_channel_config mhi_rolling_rw151_channels[] = { MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), - MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), - MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 0), MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 0), MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),@@ -986,6 +987,7 @@ static const struct mhi_pci_dev_info mhi_rolling_rw151_info = { .bar_num = MHI_PCI_DEFAULT_BAR_NUM, .dma_data_width = 32, .sideband_wake = false, + .no_m3 = true, .mru_default = 32768, .edl_trigger = true, }; --2.50.0