[PATCH net-next 15/15] net: enetc: generate MR interrupt mask based on the number of enabled VFs
From: Wei Fang <wei.fang@nxp.com>
Date: 2026-05-11 08:35:59
Also in:
imx, lkml
Subsystem:
freescale enetc ethernet drivers, networking drivers, the rest · Maintainers:
Claudiu Manoil, Vladimir Oltean, Wei Fang, Clark Wang, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
The current message-receive (MR) interrupt logic relies on the fixed ENETC_PSIIER_MR_MASK constant to determine which VF MR interrupt bits to enable or disable. This is sufficient for ENETC v1, where the number of supported VFs is limited and fixed. However, ENETC v4 devices may support a different number of VFs across implementations, making a static mask inadequate: it may fail to cover valid MR interrupt sources or enable bits for non-existent VFs. To accommodate hardware with varying VF counts, replace the fixed ENETC_PSIIER_MR_MASK constant with a new parameterized macro named PSIIER_MR_MASK(num_vf), which generates the appropriate mask based on the number of enabled VFs. The macro uses GENMASK_U32(num_vf, 1) to create a mask covering bits 1 through num_vf, where bit N corresponds to VF (N-1). This preserves the existing behavior for ENETC v1 (2 VFs) while also correctly handling devices with different VF counts such as 0, 1, 3, or more VFs as found in ENETC v4 implementations. Signed-off-by: Wei Fang <wei.fang@nxp.com> --- drivers/net/ethernet/freescale/enetc/enetc_hw.h | 3 ++- drivers/net/ethernet/freescale/enetc/enetc_msg.c | 15 ++++++++------- 2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_hw.h b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
index 94f53762cea8..77dd7913d199 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
+++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h@@ -94,7 +94,8 @@ static inline u32 enetc_vsi_set_msize(u32 size) #define ENETC_SICAPR1 0x904 #define ENETC_PSIIER 0xa00 -#define ENETC_PSIIER_MR_MASK GENMASK(2, 1) +#define PSIIER_MR_MASK(num_vf) GENMASK_U32((num_vf), 1) + #define ENETC_PSIIDR 0xa08 #define ENETC_SITXIDR 0xa18 #define ENETC_SIRXIDR 0xa28
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_msg.c b/drivers/net/ethernet/freescale/enetc/enetc_msg.c
index 73e32c9b65a8..e9963ea154b0 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_msg.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_msg.c@@ -10,9 +10,9 @@ static void enetc_msg_set_mr_int(struct enetc_pf *pf, bool enable) val = enetc_rd(hw, ENETC_PSIIER); if (enable) - val |= ENETC_PSIIER_MR_MASK; + val |= PSIIER_MR_MASK(pf->num_vfs); else - val &= ~ENETC_PSIIER_MR_MASK; + val &= ~PSIIER_MR_MASK(pf->num_vfs); enetc_wr(hw, ENETC_PSIIER, val); }
@@ -162,15 +162,16 @@ static void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, static void enetc_msg_task(struct work_struct *work) { struct enetc_pf *pf = container_of(work, struct enetc_pf, msg_task); + u32 mr_mask = PSIIER_MR_MASK(pf->num_vfs); struct enetc_hw *hw = &pf->si->hw; - unsigned long mr_mask; + u32 mr_status; int i; for (;;) { - mr_mask = enetc_rd(hw, ENETC_PSIMSGRR) & ENETC_PSIMSGRR_MR_MASK; - if (!mr_mask) { + mr_status = enetc_rd(hw, ENETC_PSIMSGRR) & mr_mask; + if (!mr_status) { /* re-arm MR interrupts, w1c the IDR reg */ - enetc_wr(hw, ENETC_PSIIDR, ENETC_PSIIER_MR_MASK); + enetc_wr(hw, ENETC_PSIIDR, mr_mask); enetc_msg_set_mr_int(pf, true); return; }
@@ -179,7 +180,7 @@ static void enetc_msg_task(struct work_struct *work) union enetc_pf_msg pf_msg = {}; u32 psimsgrr; - if (!(ENETC_PSIMSGRR_MR(i) & mr_mask)) + if (!(ENETC_PSIMSGRR_MR(i) & mr_status)) continue; enetc_msg_handle_rxmsg(pf, i, &pf_msg);
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2.34.1