[PATCH net-next 2/3] net/mlx5e: RX, Pre-calculate pad value in MPWQE
From: Tariq Toukan <tariqt@nvidia.com>
Date: 2026-03-19 07:44:32
Also in:
linux-rdma, lkml
Subsystem:
mellanox ethernet driver (mlx5e), mellanox mlx5 core vpi driver, networking drivers, the rest · Maintainers:
Saeed Mahameed, Tariq Toukan, Mark Bloch, Leon Romanovsky, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
Introduce a dedicated function that calculates the needed entries padding in a UMR WQE. Use it to pre-calculate the padding value and save it on the RQ struct. Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com> --- drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 + drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 14 ++++++++++++++ drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 8 ++------ 3 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h
index d90be82a9019..6c773a75b514 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h@@ -685,6 +685,7 @@ struct mlx5e_rq { u8 min_wqe_bulk; u8 page_shift; u8 pages_per_wqe; + u8 entries_pad; u8 umr_wqebbs; u8 mtts_per_wqe; u8 umr_mode;
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index 20c24d829ee2..5a31c79cec06 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c@@ -307,6 +307,17 @@ static void mlx5e_disable_blocking_events(struct mlx5e_priv *priv) mlx5_blocking_notifier_unregister(priv->mdev, &priv->blocking_events_nb); } +static u8 mlx5e_mpwrq_umr_entries_pad(u32 entries, + enum mlx5e_mpwrq_umr_mode umr_mode) +{ + u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode); + u32 sz; + + sz = entries * umr_entry_size; + + return ALIGN(sz, MLX5_UMR_FLEX_ALIGNMENT) - sz; +} + static u16 mlx5e_mpwrq_umr_octowords(u32 entries, enum mlx5e_mpwrq_umr_mode umr_mode) { u8 umr_entry_size = mlx5e_mpwrq_umr_entry_size(umr_mode);
@@ -904,6 +915,9 @@ static int mlx5e_alloc_rq(struct mlx5e_params *params, rq->mpwqe.pages_per_wqe = mlx5e_mpwrq_pages_per_wqe(mdev, rq->mpwqe.page_shift, rq->mpwqe.umr_mode); + rq->mpwqe.entries_pad = + mlx5e_mpwrq_umr_entries_pad(rq->mpwqe.pages_per_wqe, + rq->mpwqe.umr_mode); rq->mpwqe.umr_wqebbs = mlx5e_mpwrq_umr_wqebbs(mdev, rq->mpwqe.page_shift, rq->mpwqe.umr_mode);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
index f5c0e2a0ada9..580bb51ad7ef 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c@@ -645,13 +645,9 @@ static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) /* Pad if needed, in case the value set to ucseg->xlt_octowords * in mlx5e_build_umr_wqe() needed alignment. */ - if (rq->mpwqe.pages_per_wqe & (MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT - 1)) { - int pad = ALIGN(rq->mpwqe.pages_per_wqe, MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT) - - rq->mpwqe.pages_per_wqe; - + if (rq->mpwqe.entries_pad) memset(&umr_wqe->inline_mtts[rq->mpwqe.pages_per_wqe], 0, - sizeof(*umr_wqe->inline_mtts) * pad); - } + rq->mpwqe.entries_pad); bitmap_zero(wi->skip_release_bitmap, rq->mpwqe.pages_per_wqe); wi->consumed_strides = 0;
--
2.44.0