On Mon, Mar 09, 2026 at 11:04:12AM +0800, Wei Fang wrote:

Currently the driver does not reset the producer index register (PIR) and
consumer index register (CIR) when initializing a TX BD ring. The driver
only reads the PIR and CIR and initializes the software indexes. If the
TX BD ring is reinitialized when it still contains unsent frames, its PIR
and CIR will not be equal after the reinitialization. However, the BDs
between CIR and PIR have been freed and become invalid and this can lead
to a hardware malfunction, causing the TX BD ring will not work perperly.

Since the PIR and CIR are sofeware-configurable on ENETC v4. Therefore,
the driver must reset them if they are not equal when reinitializing
the TX BD ring.

However, resetting the PIR and CIR alone is insufficient, it cannot
completely solve the problem. When a link-down event occurs while the
the TX BD ring is transmitting frames, subsequent reinitialization of
the TX BD ring may cause it to malfunction. For example, the following
steps may reproduce the problem (not 100% reproducible).

1. Unplug the cable when the TX BD ring is busy transmitting frames.
2. Disable the network interface (ifconfig eth0 down).
3. Re-enable the network interface (ifconfig eth0 up).
4. Plug in the cable, the TX BD ring may fail to transmit packets.

When the link-down event occurs, enetc4_pl_mac_link_down() only clears
PMa_COMMAND_CONFIG[TX_EN] to disable MAC transmit data path. It doesn't
set PORT[TXDIS] to 1 to flush the TX BD ring. Therefore, reinitializing
the TX BD ring at this point is unsafe. To safely reinitialize the TX BD
ring after a link-down event, we checked with the NETC IP team, a proper
Ethernet MAC graceful stop is necessary. Therefore, add the Ethernet MAC
graceful stop to the link-down event handler enetc4_pl_mac_link_down().

Fixes: 99100d0d9922 ("net: enetc: add preliminary support for i.MX95 ENETC PF")
Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
v2:
1. Remove unused register macros (ENETC_SISR and SISR_TX_BUSY)
2. Remove spurious semicolon from enetc4_mac_wait_rx_empty()
---
 drivers/net/ethernet/freescale/enetc/enetc.c  |   9 ++
 .../net/ethernet/freescale/enetc/enetc4_hw.h  |  11 ++
 .../net/ethernet/freescale/enetc/enetc4_pf.c  | 126 ++++++++++++++++--
 3 files changed, 132 insertions(+), 14 deletions(-)

Hi,

This is a not a small patch for a fix.
Could you consider splitting it up a bit?
Say one patch for the ENETC_TBPIR/ENETC_TBCIR
portion and another for the graceful stop?

The line above this hunk is:

	/* clearing PI/CI registers for Tx not supported, adjust sw indexes */

And the AI generated review reports:

  This isn't a bug, but the comment now contradicts the code. The comment
  says "clearing PI/CI registers for Tx not supported" but the code
  immediately below clears TBPIR and TBCIR for ENETC v4 hardware.

  Should the comment be updated to clarify that clearing is only
  unsupported on ENETC rev1?

 	tx_ring->next_to_use = enetc_txbdr_rd(hw, idx, ENETC_TBPIR);
 	tx_ring->next_to_clean = enetc_txbdr_rd(hw, idx, ENETC_TBCIR);
 
+	if (tx_ring->next_to_use != tx_ring->next_to_clean &&
+	    !is_enetc_rev1(si)) {
+		tx_ring->next_to_use = 0;
+		tx_ring->next_to_clean = 0;
+		enetc_txbdr_wr(hw, idx, ENETC_TBPIR, 0);
+		enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0);
+	}
+
 	/* enable Tx ints by setting pkt thr to 1 */
 	enetc_txbdr_wr(hw, idx, ENETC_TBICR0, ENETC_TBICR0_ICEN | 0x1);
 

...

...

Can this be implemented using poll_timeout_us() ?

...

+static void enetc4_mac_wait_rx_empty(struct enetc_si *si, int mac)
+{
+	u32 timeout = 0;
+
+	while (!(enetc_port_rd(&si->hw, ENETC4_PM_IEVENT(mac)) &
+		 PM_IEVENT_RX_EMPTY)) {
+		if (timeout >= 100) {
+			dev_warn(&si->pdev->dev,
+				 "MAC %d RX is not empty\n", mac);
+			break;
+		}
+
+		usleep_range(100, 110);
+		timeout++;
+	}
+}

Likewise, here.

...