Re: [PATCH net-next v5 0/3] riscv: spacemit: Add ethernet support for K3
From: Inochi Amaoto <inochiama@gmail.com>
Date: 2026-03-03 01:04:15
Also in:
linux-arm-kernel, linux-devicetree, linux-riscv, lkml, spacemit
Subsystem:
risc-v architecture, risc-v spacemit soc support, the rest · Maintainers:
Paul Walmsley, Palmer Dabbelt, Albert Ou, Yixun Lan, Linus Torvalds
On Mon, Mar 02, 2026 at 08:08:59AM -0500, Emil Renner Berthing wrote:
Quoting Inochi Amaoto (2026-02-27 08:57:14)quoted
Add initial support for ethernet controller of the Spacemit K3 SoC. This ethernet controller is almost a standard Synopsys DesignWare MAC (version 5.40a). This controller require a syscon device to configure some basic features, like interface type and internal delay.I don't know how we can accept this when it can't be tested since it still doesn't come with the device tree nodes. If you don't want it to be part of the series, just share a tree where this code is working. There are plenty of free public git hosting sites available.
It seems like you have not read my reply before, I was forbidden from opening other's patch. So some dependency can not be satisfied. For me, the only thing I can open is the ethernet device node. The other things, like clock, pinctrl and gpio devices. You should collect by yourself and I can not provide. Here is the ethernet DTS patch
diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
index b691304d4b74..1dfeef564ef3 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts@@ -5,6 +5,7 @@ */ #include "k3.dtsi" +#include "k3-pinctrl.dtsi" / { model = "SpacemiT K3 Pico-ITX";
@@ -24,6 +25,25 @@ memory@100000000 { }; }; +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_cfg>; + + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + status = "okay"; + + mdio { + phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; + }; +}; + &uart0 { status = "okay"; };
diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
new file mode 100644
index 000000000000..aa8e7cfd7efe
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi@@ -0,0 +1,56 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include <dt-bindings/gpio/gpio.h> + +#define K3_PADCONF(pin, func) (((pin) << 16) | (func)) + +&pinctrl { + gmac0_cfg: gmac0-cfg { + /* Base pins: - Used by RMII directly */ + gmac0_base_pins: gmac0-0-pins { + pinmux = <K3_PADCONF(0, 1)>, + <K3_PADCONF(1, 1)>, + <K3_PADCONF(2, 1)>, + <K3_PADCONF(3, 1)>, + <K3_PADCONF(6, 1)>, + <K3_PADCONF(7, 1)>, + <K3_PADCONF(11, 1)>, + <K3_PADCONF(12, 1)>, + <K3_PADCONF(13, 1)>; + + bias-disable; + drive-strength = <25>; + power-source = <1800>; + }; + + /* RGMII extra pins: add on top of base pins */ + gmac0_rgmii_add_pins: gmac0-1-pins { + pinmux = <K3_PADCONF(4, 1)>, + <K3_PADCONF(5, 1)>, + <K3_PADCONF(8, 1)>, + <K3_PADCONF(9, 1)>, + <K3_PADCONF(10, 1)>; + + bias-disable; + drive-strength = <25>; + power-source = <1800>; + }; + + /* Optional int pins */ + gmac0_int_pins: gmac0-3-pins { + pinmux = <K3_PADCONF(14, 1)>; + + bias-disable; + drive-strength = <25>; + power-source = <1800>; + }; + + gmac0-6-pins { + pinmux = <K3_PADCONF(15, 0)>; + + bias-disable; + drive-strength = <25>; + power-source = <1800>; + }; + }; +};
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index 6cc31e94c13a..066006826e92 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi@@ -5,6 +5,7 @@ */ #include <dt-bindings/clock/spacemit,k3-clocks.h> +#include <dt-bindings/reset/spacemit,k3-resets.h> #include <dt-bindings/interrupt-controller/irq.h> /dts-v1/;
@@ -437,6 +438,112 @@ soc: soc { dma-noncoherent; ranges; + gmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0xf>; + snps,rd_osr_lmt = <0xf>; + /* max axi burst len is 256 */ + snps,blen = <256 128 64 32 16 0 0>; + }; + + eth0: ethernet@cac80000 { + compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; + reg = <0x0 0xcac80000 0x0 0x2000>; + clocks = <&syscon_apmu CLK_APMU_EMAC0_BUS>, + <&syscon_apmu CLK_APMU_EMAC0_1588>, + <&syscon_apmu CLK_APMU_EMAC0_RGMII_TX>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + interrupt-parent = <&saplic>; + interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, + <276 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&syscon_apmu RESET_APMU_EMAC0>; + reset-names = "stmmaceth"; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + snps,aal; + snps,tso; + snps,txpbl = <8>; + snps,rxpbl = <8>; + snps,force_sf_dma_mode; + snps,axi-config = <&gmac_axi_setup>; + spacemit,apmu = <&syscon_apmu 0x3e4 0x3e8>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + eth1: ethernet@cac82000 { + compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; + reg = <0x0 0xcac82000 0x0 0x2000>; + clocks = <&syscon_apmu CLK_APMU_EMAC1_BUS>, + <&syscon_apmu CLK_APMU_EMAC1_1588>, + <&syscon_apmu CLK_APMU_EMAC1_RGMII_TX>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + interrupt-parent = <&saplic>; + interrupts = <133 IRQ_TYPE_LEVEL_HIGH>, + <277 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&syscon_apmu RESET_APMU_EMAC1>; + reset-names = "stmmaceth"; + rx-fifo-depth = <8192>; + tx-fifo-depth = <8192>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + snps,aal; + snps,tso; + snps,txpbl = <8>; + snps,rxpbl = <8>; + snps,force_sf_dma_mode; + snps,axi-config = <&gmac_axi_setup>; + spacemit,apmu = <&syscon_apmu 0x3ec 0x3f0>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + eth2: ethernet@cac8e000 { + compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; + reg = <0x0 0xcac8e000 0x0 0x2000>; + clocks = <&syscon_apmu CLK_APMU_EMAC2_BUS>, + <&syscon_apmu CLK_APMU_EMAC2_1588>, + <&syscon_apmu CLK_APMU_EMAC2_RGMII_TX>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + interrupt-parent = <&saplic>; + interrupts = <130 IRQ_TYPE_LEVEL_HIGH>, + <278 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq"; + resets = <&syscon_apmu RESET_APMU_EMAC2>; + reset-names = "stmmaceth"; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <32>; + snps,aal; + snps,tso; + snps,txpbl = <8>; + snps,rxpbl = <8>; + snps,force_sf_dma_mode; + snps,axi-config = <&gmac_axi_setup>; + spacemit,apmu = <&syscon_apmu 0x248 0x24c>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + syscon_apbc: system-controller@d4015000 { compatible = "spacemit,k3-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>;
--
2.53.0
Inochi