Am Montag, 2. März 2026, 10:24:14 CET schrieb Wei Fang:

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Am Samstag, 28. Februar 2026, 04:52:01 CET schrieb Wei Fang:

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+static int imx95_enetc_mdio_phyaddr_config(struct platform_device
+*pdev) {
+	struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
+	struct device_node *np = pdev->dev.of_node;
+	struct device *dev = &pdev->dev;
+	int bus_devfn, addr, err;
+	u32 phy_mask = 0;
+
+	err = netc_get_emdio_phy_mask(np, &phy_mask);
+	if (err) {
+		dev_err(dev, "Failed to get PHY address mask\n");
+		return err;
+	}
+
+	/* Update the port EMDIO PHY address through parsing phy

properties.

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+	 * This is needed when using the port EMDIO but it's harmless when
+	 * using the central EMDIO. So apply it on all cases.
+	 */
+	for_each_child_of_node_scoped(np, child) {
+		for_each_child_of_node_scoped(child, gchild) {
+			if (!of_device_is_compatible(gchild, "pci1131,e101"))
+				continue;
+
+			bus_devfn = netc_of_pci_get_bus_devfn(gchild);
+			if (bus_devfn < 0) {
+				dev_err(dev, "Failed to get BDF number\n");
+				return bus_devfn;
+			}
+
+			addr = netc_get_phy_addr(gchild);
+			if (addr < 0) {
+				dev_err(dev, "Failed to get PHY address\n");
+				return addr;
+			}
+
+			if (phy_mask & BIT(addr)) {

... which will break here if there is an Ethernet PHY using address 0 in
'netc_emdio' node.
See arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi node
ethernet-phy@0.

AFAIU, the PHY address 0 is a special address, below is the description of
PHYAD from IEEE 802.3 Clause 22.

A PHY that is connected to the station management entity via the
mechanical interface defined in 22.6 shall always respond to transactions
addressed to PHY Address zero <00000>. A station management entity
that is attached to multiple PHYs must have prior knowledge of the
appropriate PHY Address for each PHY.

Therefore, for most PHYs, PHY address 0 is typically used as the broadcast
address or default response address. In designs that control multiple PHYs
via EMDIO, it is recommended to avoid setting a specific PHY to address 0
to prevent bus conflicts.

I know about this special meaning, but there are hardware design which do not
take this into account.

This might cause potential issues, as all PHYs attached to the same MDIO bus will
respond to the accesses to PHY address 0.

Is that really the case? So far we didn't have any problems with
PHYAD 0 and 3 on the same bus. I did a bit of research but couldn't find any
information backing that PHYAD 0 is actually a broadcast address. All I could
find is the case with just a single PHY on a MDIO bus, defaulting to 0.

Is this problem unfixable?

Right now our problem is that the software doesn't work any more.

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If the PHY on your board does not use PHY address 0 as the broadcast address
or the default response address, then we should check the PHY address first

and

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then check the phy_mask in imx95_enetc_mdio_phyaddr_config(), just the

same

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as imx94_enetc_mdio_phyaddr_config().

I'm not sure if this is the right fix. What about the case where phy_mask is
supposed to be 0, because there are no PHY subnodes of netc_emdio. Instead
the PHY with address is a subnode of the enet_portX is supposed to have
netc_get_phy_addr() return 0 because that's the actual address. But with
the current flow from imx94_enetc_mdio_phyaddr_config() and your suggestion
for i.MX95 case we erroneously skip that node.

The hardware default value is 0, so no need to configure it. I can send a
fix patch this week.

Okay, thanks.

Best regards,
Alexander
-- 
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