On 20.02.2026 22:10, Russell King (Oracle) wrote:

On Fri, Feb 20, 2026 at 09:50:44PM +0100, Heiner Kallweit wrote:

quoted

No, BMCR_RESET usually doesn't reset configuration registers. That's why the
function is called genphy_*soft*_reset. In case your PHY behaves different,
which configuration registers does it change?

I don't think your statement is correct.

Looking at AR8035 for example, the WoL interrupt enable is doumented as
being cleared on soft reset. Smart Speed configuration also gets reset.

802.3 22.2.4.1.1 states that setting 0.15 results in the status and
control registers shall be set to their default states.

So, we should not assume that setting 0.15 will retain configuration in
the PHY - at least phylib should not assume that a call to
genphy_soft_reset will not clear the configuration registers. If we
have code in phylib that makes that assumption, phylib is buggy to
802.3.

Indeed I was wondering why c22 states "reset control registers"
whilst the PHY's I'm dealing with don't do this. At least for the
Marvell PHY's I used the spec says "resets PHY state machine".
For Realtek the spec statement was "resets BMCR and BMSR".
And often config bits are described as "becomes effective after
reset". But yes, there may be PHY's implementing exactly the c22
behavior, so we shouldn't rely on "soft" in general.