[PATCH v7 0/2] net: mhi: Add support to enable ethernet interface
From: Vivek Pernamitta <hidden>
Date: 2026-02-05 10:34:47
Also in:
linux-arm-msm, lkml
Add support to configure a new client as Ethernet type over MHI by setting "mhi_device_info.ethernet_if = true". Create a new Ethernet interface named eth%d. This complements existing NET driver support. Introduce IP_SW1, ETH0, and ETH1 network interfaces required for M-plane, NETCONF, and S-plane components. M-plane: Implement DU M-Plane software for non-real-time O-RAN management between O-DU and O-RU using NETCONF/YANG and O-RAN WG4 M-Plane YANG models. Provide capability exchange, configuration management, performance monitoring, and fault management per O-RAN.WG4.TS.MP.0-R004-v18.00. YANG model based interface aligned with O-RAN WG4 M-Plane specifications over TCP between the OAM application on the host and the DU M-Plane software running on the X100 platform. Netconf: Use NETCONF protocol for configuration operations such as fetching, modifying, and deleting network device configurations. This interface is used for IETF Netconf communication, enabling a Netconf server on the ORU to interact with a Netconf client running on the host. S-plane: Support frequency and time synchronization between O-DUs and O-RUs using Synchronous Ethernet and IEEE 1588. Assume PTP transport over L2 Ethernet (ITU-T G.8275.1) for full timing support; allow PTP over UDP/IP (ITU-T G.8275.2) with reduced reliability, as per ORAN spec O-RAN.WG4.CUS.0-R003-v12.00. To support accurate phase and time synchronization between the host (L2) and device (L1-High), the system must exchange PTP messages as raw Layer-2 Ethernet frames, because the ITU-T G.8275.1 profile operates strictly over Ethernet multicast and not over IP networks. This means the device’s PTP stack can only send and receive PTP Announce, Sync, Follow-Up, and Delay messages in native Ethernet format, not as IPv4/IPv6 packets. However, the host and device communicate only through MHI/PCIe, which provides no native Ethernet interface. Therefore, the system must implement a virtual Ethernet interface over MHI on both sides. This virtual Layer-2 link enables true Ethernet-frame transport, ensuring the device’s PTP implementation remains fully compliant with the G.8275.1 Ethernet-based timing model. The actual link between the device (QDU100) and the host is PCIe/MHI. The device has the Ethernet interface and is exposed as the MHI channel to the host. So this patch creates the Ethernet interface on the host based on the 'IP_ETH' channel so that the host can use this interface for exchanging the NETCONF packets. The patch primarily addresses host-to-DU(QDU100) communication. However, the NETCONF/M-Plane packets originating from the host will eventually be transmitted from the DU to the RU over the fronthaul, which uses Ethernet. For additional details on this architecture and data flow, refer to the O-RAN Management Plane Specification: O-RAN.WG4.MP.0-v07.00 O-RAN Alliance Working Group 4 – Management Plane Specification Chapter 4: O-RU to O-DU Interface Management Signed-off-by: Vivek Pernamitta <redacted> --- patchset link for V6 : https://lore.kernel.org/all/20251209-vdev_next-20251208_eth_v6-v6-0-80898204f5d8@quicinc.com/ (local) patchset link for V1 (first post) : https://lore.kernel.org/all/20250724-b4-eth_us-v1-0-4dff04a9a128@quicinc.com/ (local) changes to v7: - Updated to NET_NAME_ENUM while allocating netdev as per Andrew - Updated more information as per comments from Jakub and Mani changes to v6: - Removed interm variable useage as per comments from Simon and Dmirty. - Squashed gerrits 1 and 2 in single gerrit. - Added more description for M-plane, Netconf and S-plane. changes to v5: - change in email ID from "quic_vpernami@quicinc.com" to "vivek.pernamitta@oss.qualcomm.com" - Renamed to patch v5 as per comments from Manivannan - Restored to original name as per comments from Jakub - Renamed the ethernet interfce to eth%d as per Jakub --- --- Vivek Pernamitta (2): net: mhi: Enable Ethernet interface support bus: mhi: host: pci: Enable IP_SW1, IP_ETH0 and IP_ETH1 channels for QDU100 drivers/bus/mhi/host/pci_generic.c | 8 ++++ drivers/net/mhi_net.c | 75 +++++++++++++++++++++++++++++++------- 2 files changed, 70 insertions(+), 13 deletions(-) --- base-commit: 0f8a890c4524d6e4013ff225e70de2aed7e6d726 change-id: 20260205-eth_vdev_next-20260204_eth-807136ad5cd0 Best regards, -- Vivek Pernamitta [off-list ref]