On 03/02/2026 9:30, Tariq Toukan wrote:

From: Alexei Lazar <redacted>

The per-TC rate limit was restricted to 255 Gbps due to the 8-bit
max_bw_value field in the QETC register.
This limit is insufficient for newer, higher-bandwidth NICs.

Extend the rate limit by using the full 16-bit max_bw_value field.
This allows the finer 100Mbps granularity to be used for rates up to
~6.5 Tbps, instead of switching to 1Gbps granularity at higher rates.

The extended range is only used when the device advertises support
via the qetcr_qshr_max_bw_val_msb capability bit in the QCAM register.

Signed-off-by: Alexei Lazar <redacted>
Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
Reviewed-by: Gal Pressman <redacted>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>

Please ignore this one.
Mistakenly sent two similar patches (with a slight subject change).

Find the other one here:
https://lore.kernel.org/all/20260203073021.1710806-1-tariqt@nvidia.com/ (local)