[PATCH v23 13/22] sfc: get root decoder
From: <hidden>
Date: 2026-02-01 15:55:20
Also in:
linux-cxl
Subsystem:
compute express link (cxl), networking drivers, sfc network driver, the rest · Maintainers:
Davidlohr Bueso, Jonathan Cameron, Dave Jiang, Alison Schofield, Vishal Verma, Ira Weiny, Dan Williams, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Edward Cree, Linus Torvalds
From: Alejandro Lucero <redacted> Use cxl api for getting HPA (Host Physical Address) to use from a CXL root decoder. Signed-off-by: Alejandro Lucero <redacted> Reviewed-by: Martin Habets <redacted> Acked-by: Edward Cree <ecree.xilinx@gmail.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Ben Cheatham <redacted> --- drivers/cxl/cxl.h | 15 --------------- drivers/net/ethernet/sfc/Kconfig | 1 + drivers/net/ethernet/sfc/efx_cxl.c | 26 +++++++++++++++++++++++--- drivers/net/ethernet/sfc/efx_cxl.h | 1 + include/cxl/cxl.h | 15 +++++++++++++++ 5 files changed, 40 insertions(+), 18 deletions(-)
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index c7d9b2c2908f..d1b010e5e1d0 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h@@ -220,21 +220,6 @@ int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); #define CXL_RESOURCE_NONE ((resource_size_t) -1) #define CXL_TARGET_STRLEN 20 -/* - * cxl_decoder flags that define the type of memory / devices this - * decoder supports as well as configuration lock status See "CXL 2.0 - * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. - * Additionally indicate whether decoder settings were autodetected, - * user customized. - */ -#define CXL_DECODER_F_RAM BIT(0) -#define CXL_DECODER_F_PMEM BIT(1) -#define CXL_DECODER_F_TYPE2 BIT(2) -#define CXL_DECODER_F_TYPE3 BIT(3) -#define CXL_DECODER_F_LOCK BIT(4) -#define CXL_DECODER_F_ENABLE BIT(5) -#define CXL_DECODER_F_MASK GENMASK(5, 0) - enum cxl_decoder_type { CXL_DECODER_DEVMEM = 2, CXL_DECODER_HOSTONLYMEM = 3,
diff --git a/drivers/net/ethernet/sfc/Kconfig b/drivers/net/ethernet/sfc/Kconfig
index 979f2801e2a8..e959d9b4f4ce 100644
--- a/drivers/net/ethernet/sfc/Kconfig
+++ b/drivers/net/ethernet/sfc/Kconfig@@ -69,6 +69,7 @@ config SFC_MCDI_LOGGING config SFC_CXL bool "Solarflare SFC9100-family CXL support" depends on SFC && CXL_BUS >= SFC + depends on CXL_REGION default SFC help This enables SFC CXL support if the kernel is configuring CXL for
diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
index 3536eccf1b2a..1a4c1097c315 100644
--- a/drivers/net/ethernet/sfc/efx_cxl.c
+++ b/drivers/net/ethernet/sfc/efx_cxl.c@@ -18,6 +18,7 @@ int efx_cxl_init(struct efx_probe_data *probe_data) { struct efx_nic *efx = &probe_data->efx; struct pci_dev *pci_dev = efx->pci_dev; + resource_size_t max_size; struct efx_cxl *cxl; struct range range; u16 dvsec;
@@ -110,9 +111,24 @@ int efx_cxl_init(struct efx_probe_data *probe_data) return -ENOMEM; } - probe_data->cxl = cxl; + cxl->hdm_was_committed = true; + } else { + cxl->cxlrd = cxl_get_hpa_freespace(cxl->cxlmd, 1, CXL_DECODER_F_RAM | + CXL_DECODER_F_TYPE2, &max_size); + if (IS_ERR(cxl->cxlrd)) { + dev_err(&pci_dev->dev, "cxl_get_hpa_freespace failed\n"); + return PTR_ERR(cxl->cxlrd); + } + + if (max_size < EFX_CTPIO_BUFFER_SIZE) { + dev_err(&pci_dev->dev, "%s: not enough free HPA space %pap < %u\n", + __func__, &max_size, EFX_CTPIO_BUFFER_SIZE); + cxl_put_root_decoder(cxl->cxlrd); + return -ENOSPC; + } } + probe_data->cxl = cxl; return 0; }
@@ -121,8 +137,12 @@ void efx_cxl_exit(struct efx_probe_data *probe_data) if (!probe_data->cxl) return; - iounmap(probe_data->cxl->ctpio_cxl); - cxl_unregister_region(probe_data->cxl->efx_region); + if (probe_data->cxl->hdm_was_committed) { + iounmap(probe_data->cxl->ctpio_cxl); + cxl_unregister_region(probe_data->cxl->efx_region); + } else { + cxl_put_root_decoder(probe_data->cxl->cxlrd); + } } MODULE_IMPORT_NS("CXL");
diff --git a/drivers/net/ethernet/sfc/efx_cxl.h b/drivers/net/ethernet/sfc/efx_cxl.h
index 961639cef692..9a92e386695b 100644
--- a/drivers/net/ethernet/sfc/efx_cxl.h
+++ b/drivers/net/ethernet/sfc/efx_cxl.h@@ -27,6 +27,7 @@ struct efx_cxl { struct cxl_root_decoder *cxlrd; struct cxl_port *endpoint; struct cxl_endpoint_decoder *cxled; + bool hdm_was_committed; struct cxl_region *efx_region; void __iomem *ctpio_cxl; };
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index 834dc7e78934..783ad570a6eb 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h@@ -153,6 +153,21 @@ struct cxl_dpa_partition { #define CXL_NR_PARTITIONS_MAX 2 +/* + * cxl_decoder flags that define the type of memory / devices this + * decoder supports as well as configuration lock status See "CXL 2.0 + * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. + * Additionally indicate whether decoder settings were autodetected, + * user customized. + */ +#define CXL_DECODER_F_RAM BIT(0) +#define CXL_DECODER_F_PMEM BIT(1) +#define CXL_DECODER_F_TYPE2 BIT(2) +#define CXL_DECODER_F_TYPE3 BIT(3) +#define CXL_DECODER_F_LOCK BIT(4) +#define CXL_DECODER_F_ENABLE BIT(5) +#define CXL_DECODER_F_MASK GENMASK(5, 0) + struct cxl_memdev_attach { int (*probe)(struct cxl_memdev *cxlmd); };
--
2.34.1