Re: [PATCH net-next 07/15] mfd: core: add ability for cells to probe on a custom parent OF node
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: 2026-01-16 14:22:10
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On Fri, Jan 16, 2026 at 04:02:37PM +0200, Vladimir Oltean wrote:
On Fri, Jan 16, 2026 at 01:23:45PM +0000, Lee Jones wrote:quoted
Please send me the full and finalised DTS hunk.I gave it to you earlier in this thread, it is (2) from: https://lore.kernel.org/netdev/20260109121432.lu2o22iijd4i57qq@skbuf/ (local) (the actual device tree has more irrelevant properties, the above is just the relevant skeleton) With the mention that in current device trees, the "regs" node and its underlying hierachy is missing, and patch 14 from this patch set uses the of_changeset API to dynamically fill it in before calling mfd_add_devices().
I am a bit torn between not wanting to confuse you by providing
irrelevant information, and not giving the impression that those
properties are all that there is.
The ethernet-switch root node also has all DSA properties that can be
seen in the Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml
example. The above properties are all overlaid on top.
Merged together, they would look like this:
spi {
#address-cells = <1>;
#size-cells = <0>;
sw1: ethernet-switch@0 {
compatible = "nxp,sja1110a";
reg = <0>; // means "SPI chip select"
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
pcs-handle = <&sgmii1_pcs>;
};
port@2 {
reg = <2>;
pcs-handle = <&sgmii2_pcs>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@3 {
reg = <3>;
pcs-handle = <&sgmii3_pcs>;
};
sw1p4: port@4 {
reg = <4>;
pcs-handle = <&sgmii4_pcs>;
};
port@5 {
reg = <5>;
phy-handle = <&sw1_port5_base_t1_phy>;
};
port@6 {
reg = <6>;
phy-handle = <&sw1_port6_base_t1_phy>;
};
port@7 {
reg = <7>;
phy-handle = <&sw1_port7_base_t1_phy>;
};
port@8 {
reg = <8>;
phy-handle = <&sw1_port8_base_t1_phy>;
};
port@9 {
reg = <9>;
phy-handle = <&sw1_port9_base_t1_phy>;
};
port@a {
reg = <10>;
phy-handle = <&sw1_port10_base_t1_phy>;
};
};
mdios {
#address-cells = <1>;
#size-cells = <0>;
mdio@0 {
compatible = "nxp,sja1110-base-t1-mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>; // 0 has no physical meaning other than "first bus"
sw1_port5_base_t1_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
sw1_port6_base_t1_phy: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
sw1_port7_base_t1_phy: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x3>;
};
sw1_port8_base_t1_phy: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
sw1_port9_base_t1_phy: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x5>;
};
sw1_port10_base_t1_phy: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x6>;
};
};
mdio@1 {
compatible = "nxp,sja1110-base-tx-mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>; // no physical meaning other than "second bus"
ethernet-phy@0 {
reg = <0x0>;
};
};
};
/* The portion above is established binding. The portion below isn't */
regs {
#address-cells = <1>;
#size-cells = <1>;
/* The bindings of these PCS devices all come
* from Documentation/devicetree/bindings/net/pcs/snps,dw-xpcs.yaml,
* they are not defined by me.
*/
sgmii1_pcs: ethernet-pcs@705000 { // Physical meaning: untranslatable switch address space
compatible = "nxp,sja1110-pcs";
reg = <0x705000 0x1000>;
reg-names = "indirect";
};
sgmii2_pcs: ethernet-pcs@706000 {
compatible = "nxp,sja1110-pcs";
reg = <0x706000 0x1000>;
reg-names = "indirect";
rx-polarity = <PHY_POL_INVERT>; // THIS LINE is what the entire effort is for.
};
sgmii3_pcs: ethernet-pcs@707000 {
compatible = "nxp,sja1110-pcs";
reg = <0x707000 0x1000>;
reg-names = "indirect";
};
sgmii4_pcs: ethernet-pcs@708000 {
compatible = "nxp,sja1110-pcs";
reg = <0x708000 0x1000>;
reg-names = "indirect";
};
};
};
};